High-voltage switch with low output ripple for non-volatile floating-gate memories
View Patent ↗A high-voltage switch has a high-voltage input terminal, receiving a high voltage, and an output terminal. A pass transistor, having a control terminal, is connected between the high-voltage input terminal and the output terminal. The output of a voltage-multiplying circuit of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit is of a symmetrical type, has first and second charge-storage means, receiving a clock signal of a periodic type, and has a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to the clock signal.
1. A high-voltage switch, comprising:
a high-voltage input terminal connected to a first reference-voltage line to receive a high voltage that is higher than a supply voltage to the switch;
an output terminal;
a pass transistor having a first conduction terminal connected to said high-voltage input terminal, a second conduction terminal connected to said output terminal, and a control terminal;
a boosting stage having an output connected to said control terminal, and including a charge-pump, voltage-multiplying circuit; said voltage-multiplying circuit comprising first and second charge-storage elements, which receive a periodic clock signal; wherein said voltage-multiplying circuit includes a first circuit branch and a second circuit branch couplable to the output, which are symmetrical to one another and operate in phase opposition with respect to said clock signal;
a driving input terminal connected to a second reference-voltage line; and
a feedback transistor, connected between said driving input terminal and an input of said boosting stage and having a control terminal connected to said output of said boosting stage.
2. The high-voltage switch according to claim 1 , wherein said clock signal has a first half-period and a second half-period, and said output of the boosting stage is connected to said first circuit branch in the first half-period and to said second circuit branch in the second half-period.
3. The high-voltage switch according to claim 1 , wherein said voltage-multiplying circuit is a voltage-doubler circuit.
4. The high-voltage switch according to claim 1 , wherein:
said first charge-storage element includes a first boosting capacitor, receiving said clock signal on a first terminal and having a second terminal connected to a first charge-transfer node;
said second charge-storage element includes a second boosting capacitor, receiving, on a first terminal, a negated signal in phase opposition with said clock signal, and having a second terminal connected to a second charge-transfer node;
said first circuit branch comprises a first charge transistor, connecting said first charge-transfer node to an input of said boosting stage and having a control terminal connected to said second charge-transfer node, and a first discharge transistor, connecting said first charge-transfer node to said output of said boosting stage and having a control terminal connected to said second charge-transfer node; and
said second circuit branch comprises a second charge transistor, connecting said second charge-transfer node to said input of said boosting stage and having a control terminal connected to said first charge-transfer node, and a second discharge transistor, connecting said second charge-transfer node to said output of said boosting stage and having a control terminal connected to said first charge-transfer node; said first charge transistor and second charge transistor having a first type of polarity, and said first discharge transistor and second discharge transistor having a second type of polarity.
5. The high-voltage switch according to claim 1 , wherein said boosting stage comprises at least one further voltage-multiplying circuit cascaded to said voltage-multiplying circuit.
6. The high-voltage switch according to claim 1 , wherein said voltage-multiplying circuit is a voltage-tripler circuit.
7. The high-voltage switch according to claim 1 , wherein said feedback transistor is a natural transistor.
8. The high-voltage switch according to claim 1 , wherein said second reference-voltage line is set at a voltage having an absolute value not lower than said first reference-voltage line.
9. The high-voltage switch according to claim 1 , further comprising:
a supply input terminal connected to a second reference-voltage line set at a voltage lower than said first reference-voltage line;
an enabling input terminal receiving an enabling signal of a logic type; and
a turning-on transistor, connected between said supply input terminal and said input of said boosting stage and having a control terminal connected to said enabling input terminal.
10. The high-voltage switch according to claim 1 , further comprising
a first disabling input terminal and a second disabling input terminal, receiving, respectively, a first turning-off signal and a second turning-off signal;
a first turning-off transistor, connected between said input of said boosting stage and a second reference-voltage line and having a control terminal connected to said first disabling input terminal; and
a second turning-off transistor, connected between said output of said boosting stage and said second reference-voltage line and having a control terminal connected to said second disabling input terminal.
11. The high-voltage switch according to claim 1 , wherein said clock signal has a frequency which can be adjusted.
12. A floating-gate non-volatile memory device, comprising:
an array of memory cells; and
a first high-voltage switch that includes:
a high-voltage input terminal connected to a first reference-voltage line;
an output terminal;
a pass transistor having a first conduction terminal connected to said high-voltage input terminal, a second conduction terminal connected to said output terminal, and a control terminal;
a boosting stage having an output connected to said control terminal, and including a charge-pump, voltage-multiplying circuit; said voltage-multiplying circuit comprising first and second charge-storage elements, which receive a periodic clock signal;
wherein said voltage-multiplying circuit includes a first circuit branch and a second circuit branch, which are symmetrical to one another and operate in phase opposition with respect to said clock signal;
a driving input terminal connected to a second reference-voltage line; and
a feedback transistor, connected between said driving input terminal and an input of said boosting stage and having a control terminal connected to said output of said boosting stage.
13. The memory device according to claim 12 , wherein the array of memory cells is organized in a plurality of wordlines and bitlines, the device further comprising:
a row decoder connected to said wordlines and including a first plurality of high-voltage switches connected to the wordlines, respectively; and
a column decoder connected to said bitlines and including a second plurality of high-voltage switches connected to said bitlines, respectively, wherein the first high-voltage switches is one of the high-voltage switches in the first and second pluralities.
14. The memory device according to claim 12 , wherein:
the first charge-storage element includes a first boosting capacitor, receiving the clock signal on a first terminal and having a second terminal connected to a first charge-transfer node;
the second charge-storage element includes a second boosting capacitor, receiving, on a first terminal, a negated signal in phase opposition with the clock signal, and having a second terminal connected to a second charge-transfer node;
the first circuit branch comprises a first charge transistor, connecting the first charge-transfer node to the input of the boosting stage and having a control terminal connected to the second charge-transfer node, and a first discharge transistor, connecting the first charge-transfer node to the output of the boosting stage and having a control terminal connected to the second charge-transfer node; and
the second circuit branch comprises a second charge transistor, connecting the second charge-transfer node to the input of the boosting stage and having a control terminal connected to the first charge-transfer node, and a second discharge transistor, connecting the second charge-transfer node to the output of the boosting stage and having a control terminal connected to the first charge-transfer node; the first charge transistor and second charge transistor having a first type of polarity, and the first discharge transistor and second discharge transistor having a second type of polarity.
15. A high-voltage switch, comprising
a high-voltage input terminal connected to a first reference-voltage line to receive a high voltage that is greater than a supply voltage;
an output terminal;
a pass transistor having a first conduction terminal connected to the high-voltage input terminal, a second conduction terminal connected to the output terminal, and a control terminal;
a boosting stage including:
an input receiving a voltage to be boosted;
an output connected to the control terminal;
first and second charge-storage elements connected to first and second charge-transfer nodes, respectively;
a first charge transistor connected between the input and the first charge-transfer node;
a second charge transistor connected between the input and the second charge-transfer node;
a driving input terminal connected to a second reference-voltage line; and
a feedback transistor connected between the driving input terminal and the input of the boosting stage and having a control terminal connected to the output of the boosting stage, the feedback transistor further coupled to the second reference voltage line.
16. The high-voltage switch according to claim 15 , further comprising:
a first discharge transistor connecting the first charge-transfer node to the output of the boosting stage and having a control terminal connected to the second charge-transfer node; and
a second discharge transistor connecting the second charge-transfer node to the output of the boosting stage and having a control terminal connected to the first charge-transfer node.
17. The high-voltage switch according to claim 15 , further comprising:
a first biasing transistor having a first conduction terminal, a second conduction terminal connected to the first charge-transfer node, a control terminal connected to the second charge-transfer node, and a bulk terminal connected to a bulk terminal of the first charge transistor; and
a second biasing transistor having a first conduction terminal connected to the first conduction terminal of the first biasing transistor, a second conduction terminal connected to the second charge-transfer node, a control terminal connected to the first charge-transfer node, and a bulk terminal connected to a bulk terminal of the second charge transistor.
18. The high-voltage switch according to claim 15 , wherein the first charge-storage element is connected between a first clock input and the first charge-transfer node and the second charge-storage element is connected between a second clock input and the second charge-transfer node, the second clock input receiving a clock signal that is inverted compared to a clock signal at the first clock input.
19. The high-voltage switch according to claim 15 , wherein the feedback transistor is a natural transistor.
20. The high-voltage switch according to claim 15 , wherein the second reference-voltage line is set at a voltage having an absolute value not lower than the first reference-voltage line.
21. The high-voltage switch according to claim 15 , further comprising:
a supply input terminal connected to a third reference-voltage line set at a voltage lower than the first reference-voltage line;
an enabling input terminal receiving an enabling signal of a logic type; and
an enabling transistor connected between the supply input terminal and the input of the boosting stage and having a control terminal connected to the enabling input terminal.
22. The high-voltage switch according to claim 15 , further comprising
a first disabling input terminal and a second disabling input terminal, receiving, respectively, a first disabling signal and a second disabling signal;
a first disabling transistor connected between the input of the boosting stage and a third reference-voltage line and having a control terminal connected to the first disabling input terminal; and
a second disabling transistor connected between the output of the boosting stage and the third reference-voltage line and having a control terminal connected to the second disabling input terminal.