Embedded chip package with improved heat dissipation performance and method of making the same
A Chip-in Substrate Package (CiSP) includes a double-sided metal clad laminate including a dielectric interposer, a first metal foil laminated on a first side of the dielectric interposer, and a second metal foil laminated on a second side of the dielectric interposer. A recessed cavity is etched into the second metal foil and the dielectric interposer with a portion of the first metal foil as its bottom. A die is mounted within the recessed cavity and makes thermal contact with the first metal foil. A build-up material layer covers the second metal foil and an active surface of the die. The build-up material layer also fills the gap between the die and the dielectric interposer. At least one interconnection layer is provided on the build-up material layer and is electrically connected with a bonding pad disposed on the active surface of the die via a plated through hole.
1. An embedded chip package with improved heat dissipation performance comprising:
a double-sided substrate comprising a dielectric interposer, a first metal foil positioned on a first surface of the dielectric interposer, and a second metal foil directly contacting a second surface of the dielectric interposer;
a recessed cavity formed in the second metal foil and the dielectric interposer, and the recessed cavity has a bottom on the first metal foil;
a die positioned in the recessed cavity having a bottom contacting thermally with the first metal foil;
a build-up material layer covering the second metal foil and an active surface of the die, the build-up material layer filling in the gap between the side of the die and the dielectric interposer;
a bonding pad disposed on the active surface of the die;
at least one first interconnect layer on the build-up material layer, and the first interconnect layer being directly above the bonding pad; and
a first conductive via electrically coupling to the first interconnect layer and the bonding pad; wherein heat generated on the die during operation conducts through the first metal foil to an external environment.
2. The embedded chip package of claim 1 , wherein the dielectric interposer comprises glass fiber or resin.
3. The embedded chip package of claim 1 further comprises an adhesive layer positioned between the bottom of the die and the first metal foil.
4. The embedded chip package of claim 3 , wherein the adhesive layer comprises a heat dissipating glue.
5. The embedded chip package of claim 1 , wherein the adhesive layer comprises Ajinomoto Build-Up, epoxy resin or prepreg.
6. The embedded chip package of claim 1 further comprising a solder resist layer positioned on the first interconnect layer.
7. The embedded chip package of claim 6 , wherein the solder resist layer comprises at least a first opening for exposing a part of the first interconnect layer, and a first bump is positioned inside the first opening.
8. The embedded chip of claim 1 , wherein the die is positioned directly on a surface of the first metal foil.
9. The embedded chip package of claim 1 , further comprising at least one second interconnect layer on the build-up material layer, wherein the second interconnect layer is at the same plane with the first interconnect layer, and a second conductive via electrically couples to the second interconnect layer and the second metal foil.
10. The embedded chip package of claim 7 , further comprising at least one second interconnect layer on the build-up material layer, wherein the second interconnect layer is at the same plane with the first interconnect layer, and a second conductive via electrically couples to the second interconnect layer and the second metal foil.
11. The embedded chip package of claim 10 , wherein the solder resist layer comprises at least an second opening for exposing a part of the second interconnect layer, and a second bump is positioned inside the second opening.