System and method for direct etching
View Patent ↗System and method for direct etching. According to an embodiment, the present invention provides a method for manufacturing an integrated circuit device. The method includes a step for providing a substrate having a contact region, which is provided between a first word line and a second word line. The contact region has an overlying plug structure, which is provided within a thickness of a first dielectric layer. The first dielectric layer includes a portion overlying the plug structure. The first dielectric layer has a planarized surface region. The method also includes a step for forming a first line and a second line and a space provided between the first word line and the second world line. The space is provided within a region overlying the plug structure.
1. A method for manufacturing an integrated circuit device, the method comprising:
providing a substrate having a contact region, the contact region provided between a first word line and a second word line, the contact region having an overlying plug structure, the plug structure being provided within a thickness of a first dielectric layer, the first dielectric layer including a portion overlying the plug structure, the first dielectric layer having a planarized surface region;
forming a first line and a second line and a space provided between the first word line and the second word line, the space being provided within a region overlying the plug structure;
forming a plurality of spacers, the plurality of spacers including a first spacer overlaying the first line and a second spacer overlaying the second line, the first spacer being characterized by a width and a height;
forming a second dielectric layer overlying the plurality of spacers;
planarizing the second dielectric layer;
forming a hard mask;
patterning the hard mask to form a first exposed region;
forming a thickness of spacer material;
performing anisotropic etching the thickness of the spacer material to form a second exposed region within the first exposed region, the second exposed region being defined by a first sidewall spacer on a first edge of the first exposed region and a second sidewall spacer on a second edge of the first exposed region;
performing an etching process within the second exposed region at a depth to form an opening, the etching process removing at least a portion of the dielectric layer; and
forming a contact within the opening.
2. The method of claim 1 wherein the contact comprises polysilicon material.
3. The method of claim 1 wherein the first line comprises tungsten material.
4. The method of claim 1 wherein the first line comprises a bit line.
5. The method of claim 1 wherein the first line comprises a word line.
6. The method of claim 1 further comprising removing the hard mask.
7. The method of claim 1 further comprising removing the first sidewall spacer.
8. The method of claim 1 wherein the width is less than 120 angstroms.
9. The method of claim 1 wherein the width is approximately 120 angstroms.
10. The method of claim 1 wherein the etching process does not remove the contact material.
11. A method for manufacturing an integrated circuit device, the method comprising:
providing a substrate having a contact region, the contact region provided between a first word line and a second word line, the contact region having an overlying plug structure, the plug structure being provided within a thickness of a first dielectric layer, the first dielectric layer including a portion overlying the plug structure, the first dielectric layer having a planarized surface region;
forming a first line and a second line and a space provided between the first word line and the second word line, the space being provided within a region overlying the plug structure;
forming a plurality of spacers, the plurality of spacers including a first spacer overlaying the first line and a second spacer overlaying the second line, the first spacer being characterized by a width and a height;
forming a second dielectric layer overlying the plurality of spacers;
forming a hard mask overlaying the dielectric layer;
patterning the hard mask to form a first exposed region;
forming a thickness of spacer material;
forming a second exposed region within the first exposed region, the second exposed region being defined by a first sidewall spacer on a first edge of the first exposed region and a second sidewall spacer on a second edge of the first exposed region;
performing an etching process within the second exposed region at a depth to form an opening, the etching process removing at least a portion of the dielectric layer;
forming a contact within the opening; and
removing the hard mask.
12. The method of claim 1 wherein the contact comprises polysilicon material.
13. The method of claim 1 wherein the contact comprises tungsten material.
14. The method of claim 1 wherein the second dielectric layer comprises silicon oxide material.
15. The method of claim 1 wherein the first sidewall spacer comprise polysilicon material.
16. The method of claim 1 wherein the hard mask comprise polysilicon material.