IP Library › Granted Patent US 7,538,009
Granted Patent B2
US 7,538,009 · App. 11/616,305 · Granted May 26, 2009

Method for fabricating STI gap fill oxide layer in semiconductor devices

Assignee: Dongbu Electronics Co., Ltd.
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Quick Facts
Patent No.
US 7,538,009
App. No.
11/616,305
Granted
May 26, 2009
Kind
B2
Abstract

A method for fabricating an STI gap fill oxide layer in a semiconductor device is provided. The method can include: forming a shallow trench for forming an STI on a semiconductor substrate; forming an STI liner oxide layer in the shallow trench for the STI; depositing an APCVD oxide layer at an upper portion of the STI liner oxide layer for an oxide layer gap fill in the shallow trench of the STI; d) performing a densifying annealing process to densify the APCVD oxide layer; and depositing an HDP-CVD oxide layer at an upper portion of the APCVD oxide layer so that the STI shallow trench is completely gap-filled.

Claims (18)

1. A method for fabricating an STI gap fill oxide layer for a semiconductor device, comprising:

forming a shallow trench for forming an STI on a semiconductor substrate;

forming an STI liner oxide layer in the shallow trench for the STI;

depositing an APCVD oxide layer on the STI liner oxide layer for an oxide layer gap fill in the shallow trench of the STI;

performing a densifying annealing process to densify the APCVD oxide layer; and

depositing an HDP-CVD oxide layer on the APCVD oxide layer so that the STI shallow trench is completely gap-filled,

wherein depositing the APCVD oxide layer comprises:

loading the semiconductor on a belt moving below a plurality of APCVD oxide layer deposition injectors; and

sequentially depositing the APCVD oxide layer using the plurality of APCVD oxide layer deposition injectors, the APCVD oxide layer having a lamination structure corresponding to the number of the injectors,

wherein the plurality of APCVD oxide layer deposition injectors includes first, second, third, and fourth injectors, which are installed along a moving path of the semiconductor loaded on the belt,

wherein the first and second injectors perform an APCVD oxide layer deposition at a temperature higher than that of the third and fourth injectors to perform a surface reaction between first and second laminate APCVD oxide layers to the STI liner oxide layer.

2. The method according to claim 1 , wherein the STI liner oxide layer is formed by a thermal treatment process.

3. The method according to claim 1 , wherein the APCVD oxide layer deposition temperature of the first and second injectors is 530° C.

4. The method according to claim 1 , wherein the APCVD oxide layer deposition temperature of the third and fourth injectors is 500° C.

5. The method according to claim 1 , wherein a material of the APCVD oxide layer deposited by the injectors is O 3 TEOS.

6. The method according to claim 5 , wherein the O 3 TEOS flown in the injectors has a concentration of 80 g/m 3 .

7. The method according to claim 1 , wherein the APCVD oxide layer of a laminate construction having four layers has a thickness ranging from 2500 to 5000 Å.

8. The method according to claim 1 , wherein the densifying annealing process of the APCVD oxide layer is performed at a temperature of 1000° C.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2007
From: KIM, SUNG RAE
To: DONGBU ELECTRONICS, CO., LTD.
Reel/Frame 018964/0819 →
Priority Claims (1)
KR 10-2005-0131447 · Dec 28, 2005 · national
Continuity (1)
Related Publication 20070148903A1 · Jun 28, 2007