Isolation circuit
The present disclosure includes various method, device, and system embodiments for isolation circuits. One such isolation circuit embodiment includes: a first transistor having its source connected to a first terminal, wherein the first terminal connects a supply voltage to the source of the first transistor; a register connected to the drain of the first transistor; and a second transistor in parallel with a resistor, the gate of the second transistor is connected to an output of the register and a source of the second transistor is connected to the first terminal. In various embodiments, the drain of the second transistor is connected to a second terminal and the state of the second transistor depends on whether the register is loaded.
1. An isolation circuit, comprising:
an on-die resistor stack having an input connected to a first voltage supply pad of a semiconductor die and an output signal connected to a second voltage supply pad of the semiconductor die, the first supply pad being connected to an external power supply, wherein the resistor stack includes a number of levels including:
a first level having a first resistor connected to a source of a first transistor, a gate of the first transistor being connected to a first enable input;
a second level having a second resistor connected to a source of a second transistor, a gate of the second transistor being connected to a second enable input; and
wherein the first and second enable inputs are controlled to set a resistance value of the resistor stack in order to limit a current value drawn by the die through the resistor stack during a testing operation.
2. The circuit of claim 1 , wherein the first enable input is controlled by a first register and the second enable input is controlled by a second register in order to set the resistance value of the resistor stack.
3. The circuit of claim 1 , wherein the first resistor is connected in series with the first transistor and the second resistor is connected in series with the second transistor.
4. The circuit of claim 3 , wherein the first and second levels are parallel to each other.
5. The circuit of claim 3 , wherein the resistor stack includes a third level that includes a third resistor connected to a source of a third transistor, a gate of the third transistor is connected to a third enable input.
6. The circuit of claim 1 , wherein the second voltage supply pad is a built in self stress (BISS) supply pad and the testing operation is a BISS testing operation.
7. The circuit of claim 1 , wherein the second voltage supply pad is a bum-in pad and the testing operation is a wafer level burn-in (WLB) testing operation.
8. The circuit of claim 1 , wherein the resistance value of the resistor stack is set to a first value when the first voltage supply pad is shorted and is set to a different value when the first voltage supply pad is not shorted.