Multi-operational mode transistor with multiple-channel device structure
A multiple operating mode transistor is provided in which multiple channels having different respective operational characteristics are employed. Multiple channels have threshold voltages that are independently adjustable. The independent adjustment of the threshold voltage includes providing at least one of different respective doping concentrations in the different channels, different respective gate dielectric thicknesses for the different gate dielectrics separating the channels, and different respective silicon channel thicknesses for the different channels.
1. A method of forming a semiconductor device, comprising the steps of: forming multiple adjacent channels;
doping each of the multiple adjacent channels with the same conductivity type;
forming a gate electrode on the multiple adjacent channels; and
independently adjusting the threshold voltage for each channel;
wherein the step of forming multiple channels includes forming a first gate dielectric, a first silicon channel on the first gate dielectric, a second gate dielectric on the first silicon channel, a second silicon channel on the second date dielectric, and a third gate dielectric on the second channel.
2. The method of claim 1 , wherein the step of independently adjusting the threshold voltage includes providing different respective dopant concentrations in the first and second channels.
3. The method of claim 1 , wherein the step of independently adjusting the threshold voltage includes providing different respective gate dielectric thicknesses for the first, second and third gate dielectrics.
4. The method of claim 1 , wherein the step of independently adjusting the threshold voltage includes providing different respective silicon channel thicknesses for the first and second channels.
5. The method of claim 1 , wherein the step of independently adjusting the threshold voltage includes providing at least one of: different respective dopant concentrations in the first and second channels; different respective gate dielectric thicknesses for the first, second and their gate dielectrics; and different respective silicon channel thicknesses for the first and second silicon channels.
6. The method of claim 5 , wherein the step of independently adjusting the threshold voltage for each channel includes adjusting the threshold voltages sufficiently differently such that application of a specified gate voltage will turn on one of the first and second channels while the other of the first and second channels remains off.
7. The method of claim 6 , further comprising controlling a drive current to a specified value by controlling the number of the first and second channels turned on and off.
8. A method of forming a multiple operating mode transistor, comprising the steps of:
forming multiple adjacent channels, each channel being doped with the same conductivity type, at least one of the channels having different operational parameters than at least one of the other channels; and
forming a gate electrode on the multiple channels,
wherein the step of forming multiple channels includes forming multiple silicon channels separated from each other and the gate electrode by gate dielectric layers.
9. The method of claim 8 , wherein at least some of the multiple silicon channels are formed with different respective thicknesses.
10. The method of claim 9 , wherein at least some of the gate dielectric layers are formed with different respective thicknesses.
11. The method of claim 10 , wherein at least some of the silicon channels are doped with different respective dopant concentrations.
12. The method of claim 8 , wherein the multiple channels are formed with independent control for each channel of at least one of: gate dielectric thickness; dopant concentration in the silicon channels; and thickness of the silicon channels.
13. A method of forming a semiconductor device, comprising the steps of:
forming multiple adjacent channels, with each adjacent channel being doped the same conductivity type;
forming a gate electrode on the multiple channels; and
independently adjusting a threshold voltage for each channel.
14. The method of claim 13 , wherein the step of forming multiple channels includes forming a first gate dielectric, a first silicon channel on the first gate dielectric, a second gate dielectric on the first silicon channel, a second silicon channel on the second date dielectric, and a third gate dielectric on the second channel.
15. The method of claim 13 , wherein the step of independently adjusting the threshold voltage includes providing different respective dopant concentrations in the first and second channels.
16. The method of claim 13 , wherein the step of independently adjusting the threshold voltage includes providing different respective gate dielectric thicknesses for the first, second and third gate dielectrics.
17. The method of claim 13 , wherein the step of independently adjusting the threshold voltage includes providing different respective silicon channel thicknesses for the first and second channels.
18. The method of claim 13 , wherein the step of independently adjusting the threshold voltage includes providing at least one of: different respective dopant concentrations in the first and second channels; different respective gate dielectric thicknesses for the first, second and their gate dielectrics; and different respective silicon channel thicknesses for the first and second silicon channels.
19. The method of claim 13 , wherein the step of independently adjusting the threshold voltage for each channel includes adjusting the threshold voltages sufficiently differently such that application of a specified gate voltage will turn on one of the first and second channels while the other of the first and second channels remains off.
20. The method of claim 19 , further comprising controlling a drive current to a specified value by controlling the number of the first and second channels turned on and off.
21. A method of forming a multiple operating mode transistor, comprising the steps of:
forming multiple adjacent channels, each adjacent channel being doped with the same conductivity type, at least one of the channels having different operational parameters than at least one of the other channels; and
forming a gate electrode on the channels.
22. The method of claim 21 , wherein the step of forming multiple channels includes forming multiple silicon channels separated from each other and the gate electrode by gate dielectric layers.
23. The method of claim 22 , wherein at least some of the multiple silicon channels are formed with different respective thicknesses.
24. The method of claim 23 , wherein at least some of the gate dielectric layers are formed with different respective thicknesses.
25. The method of claim 22 , wherein at least some of the silicon channels are doped with different respective dopant concentrations.
26. The method of claim 21 , wherein the multiple channels are formed with independent control for each channel of at least one of: gate dielectric thickness; dopant concentration in the silicon channels; and thickness of the silicon channels.