Data strobe synchronization circuit and method for double data rate, multi-bit writes
A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.
1. A control circuit coupled to a first logic circuit and a second logic circuit, the control circuit operable to receive a write control signal and operable to generate a first enable signal and a second enable signal, the second enable signal being generated in response to receiving the write control signal and after generating the first enable signal, the control circuit further operable to enable the first logic circuit by coupling the first enable signal to the first logic circuit, disable the first logic circuit by coupling the second enable signal to the second logic circuit, and terminate the first enable signal when the second enable signal is generated.
2. The control circuit of claim 1 wherein the control circuit comprises a flip flop operable to be set and reset in response to a transition of a signal being applied to an input of the flip flop, the first logic circuit being enabled in response to the flip flop being set or reset.
3. The control circuit of claim 2 wherein the input of the flip flop comprises a clock input so that a signal applied to the clock input sets or resets the flip flop by toggling the flip flop.
4. A data strobe input circuit comprising:
a first data capture circuit operable to capture data responsive to a first local data strobe signal;
a second data capture circuit operable to capture data responsive to a second local data strobe signal; and
a control circuit coupled to the first and second data capture circuits, the control circuit operable to receive a first global data strobe signal and a write control signal, the control circuit further being operable to generate the first local data strobe signal, the first local data strobe signal applied to the first data capture circuit in response to the write control signal being active, the control circuit further operable to receive a second global data strobe signal and generate the second local data strobe signal, the second local data strobe signal applied to the second data capture circuit in response to the write control signal being inactive.
5. The data strobe input circuit of claim 4 wherein the control circuit is operable to generate a first enable signal when the write control signal is active, the first enable signal being operable to enable the first data capture circuit.
6. The data strobe input circuit of claim 4 wherein the control circuit is operable to generate a second enable signal when the write control signal is inactive, the second enable signal being operable to enable the second data capture circuit.
7. A flip flop coupled to a first and second logic circuit, the flip flop operable to disable the first logic circuit and enable the second logic circuit by generating a first local data strobe signal in response to receiving a first global data strobe signal and a write control signal, the flip flop reset by enabling the first logic circuit and disabling the second logic circuit, wherein the act of enabling the first logic circuit and disabling the second logic circuit comprises generating a second local data strobe signal in response to receiving a second global data strobe signal and a subsequent write control signal.
8. The flip flop of claim 7 wherein the act of disabling the first logic circuit comprises toggling the flip flop.
9. The flip flop of claim 7 wherein the first and second logic circuits comprise flip flops.
10. A method of toggling between logic circuits comprising:
while a write control signal is in a first state, generating a first data strobe pulse in response to a first transition of a first data strobe signal, and in response to the first data strobe pulse enabling a first logic circuit;
while the write control signal is in the first state, suppressing a subsequent data strobe pulse in response to a first transition of a second data strobe signal; and
while the write control signal is in a second state, generating a second data strobe pulse in response to a second transition of the second data strobe signal, and in response to the second data strobe pulse disabling the first logic circuit and enabling a second logic circuit.
11. The method of claim 10 wherein the first transition of a second data strobe signal is generated in response to a noise pulse.
12. The method of claim 10 wherein the transition of the first data strobe signal is generated in response to a global data signal.
13. The method of claim 10 wherein the transition of the second data strobe signal is generated in response to a global data signal.
14. The method of claim 10 wherein the first transition of the second data strobe signal causes data to be latched to the first storage device.