IP Library Granted Patent US 7,569,421
Granted Patent B2
US 7,569,421 · App. 11/744,657 · Granted Aug 4, 2009

Through-hole via on saw streets

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,569,421
App. No.
11/744,657
Granted
Aug 4, 2009
Kind
B2
Abstract

A semiconductor device is manufactured by, first, providing a wafer designated with a saw street guide. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A plurality of via holes is formed in the organic material. Each of the plurality of via holes is patterned to each of a plurality of bond pad locations on the plurality of dies. A conductive material is deposited in each of the plurality of via holes.

Claims (53)

1. A method of manufacturing a semiconductor device, comprising:

providing a wafer designated with a saw street guide;

taping the wafer with a dicing tape;

singulating the wafer along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies;

stretching the dicing tape to expand the plurality of gaps to a predetermined distance;

depositing an organic material into each of the plurality of gaps, wherein a top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies;

forming a plurality of via holes in the organic material;

patterning each of the plurality of via holes to each of a plurality of bond pad locations on the plurality of dies;

depositing a conductive material in each of the plurality of via holes; and

singulating each of the plurality of dies from the dicing tape.

2. The method of manufacture of claim 1 , wherein the organic material includes a benzocyclobutene (BCB), polyimide (PI), or acrylic resin material.

3. The method of manufacture of claim 1 , wherein the organic material is applied using a spin coating or needle dispensing process.

4. The method of manufacture of claim 1 , wherein the plurality of via holes is formed in the organic material using a laser via drilling process or etching process.

5. The method of manufacture of claim 1 , wherein stretching the dicing tape to expand the plurality of gaps to a predetermined distance is performed using an expansion table.

6. The method of manufacture of claim 1 , further including picking each of the plurality of dies from the dicing tape.

7. A method of manufacturing a semiconductor device, comprising:

providing a wafer designated with a saw street guide;

taping the wafer with a first dicing tape;

singulating the wafer along the saw street guide into a plurality of dies having a plurality of first gaps between each of the plurality of dies;

picking the plurality of dies from the first dicing tape;

placing the plurality of dies onto a first wafer support system to obtain a plurality of second gaps of a predetermined width between each of the plurality of dies;

depositing an organic material into each of the plurality of gaps to render a recoated wafer, wherein a top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies;

transferring the recoated wafer onto a second wafer support system;

forming a plurality of via holes in the organic material;

patterning each of the plurality of via holes to each of a plurality of bond pad locations on the plurality of dies;

depositing a conductive material in each of the plurality of via holes;

transferring the recoated wafer onto a second dicing tape; and

singulating each of the plurality of dies from the second dicing tape.

8. The method of manufacture of claim 7 , wherein the first wafer support system comprises a third dicing tape.

9. The method of manufacture of claim 7 , wherein the first or second wafer support systems include a glass, silicon, or ceramic substrate.

10. The method of manufacture of claim 7 , wherein the organic material includes a benzocyclobutene (BCB), polyimide (PI), or acrylic resin material.

11. The method of manufacture of claim 7 , wherein the organic material is applied using a spin coating or needle dispensing process.

12. The method of manufacture of claim 7 , wherein the plurality of via holes is formed in the organic material using a laser via drilling process or etching process.

13. The method of manufacture of claim 7 , further including picking each of the plurality of dies from the second dicing tape.

14. A method of manufacturing a semiconductor device, comprising:

providing a first die having top, bottom, and peripheral surfaces;

providing a bond pad formed over the top surface;

providing an organic material connected to the first die and disposed around the peripheral surface;

providing a via hole formed in the organic material;

providing a metal trace connecting the via hole to the bond pad; and

providing a conductive material deposited in the via hole.

15. The method of manufacture of claim 14 , wherein the organic material includes a benzocyclobutene (BCB), polyimide (PI), or acrylic resin material.

16. The method of manufacture of claim 14 , wherein the first die is singulated from a plurality of dies along a saw street guide.

17. The method of manufacture of claim 14 , wherein the organic material is applied using a spin coating or needle dispensing process.

18. The method of manufacture of claim 14 , wherein the via hole is formed in the organic material using a laser via drilling process or etching process.

19. The method of manufacture of claim 14 , further including providing a second die stacked above the first die.

20. The method of manufacture of claim 19 , wherein the second die is stacked above the first die using a direct via metal bonding process or a solder paste.

21. The method of manufacture of claim 14 , further including:

providing a plurality of additional bond pads, formed over the top surface of the first die and oriented along a bond pad row, and

providing a plurality of additional via holes, formed in the organic material and oriented along a via hole row.

22. The method of manufacture of claim 14 , further including providing a dummy via hole to connect an additional semiconductor device, act as a ground, or transfer input/output (I/O) signals.

23. The method of manufacture of claim 22 , wherein the dummy hole is oriented on a first side of the peripheral surface, or oriented on a first side and an opposing side of the peripheral surface.

24. The method of manufacture of claim 16 , wherein the via hole is half-cut or complete, depending on an orientation of the saw street guide.

Assignments (5)
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052935/0327 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2007
From: DO, BYUNG TAI; KUAN, HEAP HOE
To: STATS CHIPPAC, LTD.
Reel/Frame 019251/0668 →