IP Library › Granted Patent US 7,588,988
Granted Patent B2
US 7,588,988 · App. 10/931,533 · Granted Sep 15, 2009

Method of forming apparatus having oxide films formed using atomic layer deposition

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,588,988
App. No.
10/931,533
Granted
Sep 15, 2009
Kind
B2
Abstract

A dielectric layer containing an atomic layer deposited insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric layer produce a reliable dielectric layer for use in a variety of electronic devices. Embodiments include conducting a number of annealing processes between a number of atomic layer deposition cycles for forming the metal oxide film. In an embodiment, a titanium aluminum oxide film is formed. Embodiments include structures for capacitors, transistors, memory devices, and electronic systems with dielectric layers containing an atomic layer deposited titanium aluminum oxide film, and methods for forming such structures.

Claims (107)

1. A method comprising:

forming a dielectric layer containing an insulating metal oxide in an integrated circuit, the insulating metal oxide being a bimetal oxide, ABO x , with A being a first metal and B being a second metal, forming of the insulating metal oxide including:

forming a first layer by atomic layer deposition using two or more atomic layer deposition cycles, the first layer being a metal layer including the first metal or the second metal or both the first metal and the second metal;

annealing the first layer using oxygen to convert the first layer of an oxide layer;

forming, after annealing the first layer, a second layer onto and contacting the oxygen annealed first layer using atomic layer deposition, the second layer being an insulating metal oxide including the first metal or the second metal or both the first metal and the second metal; and

processing the first and the second layer such that the oxygen annealed first layer and the second layer form contiguous layers of the bimetal metal oxide.

2. The method of claim 1 , wherein annealing the first layer using oxygen includes annealing the first layer substantially using atomic oxygen.

3. The method of claim 1 , wherein forming a first layer includes forming the first layer as a layer of the first metal and the second metal.

4. The method of claim 1 , forming a first layer includes forming the first layer having a thickness of about one monolayer.

5. The method of claim 1 , forming a first layer includes forming the first layer having a thickness of at most substantially two monolayers.

6. The method of claim 1 , wherein forming and processing the second layer includes:

depositing the first metal and/or the second metal on the first layer by atomic layer deposition; and

annealing the deposited first metal and/or the second metal using oxygen.

7. A method comprising:

forming a dielectric layer containing a titanium aluminum oxide film in an integrated circuit, the titanium aluminum oxide being a bimetal oxide (TiAlO x ), the forming of the titanium aluminum oxide film including:

forming a first layer of at least one of titanium and aluminum by atomic layer deposition using two or more atomic layer deposition cycles;

annealing the first layer using oxygen to convert the first layer to an oxide layer; and

forming a second layer, the second layer being a layer of titanium aluminim oxide, the second layer formed onto and contacting the first layer by atomic layer deposition, after annealing the first layer, to form contiguous layers of titanium aluminum oxide.

8. The method of claim 7 , wherein annealing the first layer using oxygen includes annealing the first layer substantially using atomic oxygen.

9. The method of claim 7 , wherein forming a first layer includes forming the first layer as a layer of titanium and aluminum.

10. The method of claim 7 , wherein forming a second layer of titanium aluminum oxide includes:

depositing at least one of titanium or aluminum on the first layer by atomic layer deposition; and

annealing the deposited at least one of titanium or aluminum using oxygen.

11. The method of claim 7 , wherein forming a first layer of at least one of titanium or aluminum and annealing the first layer includes:

depositing titanium by atomic layer deposition;

annealing the deposited titanium using oxygen;

depositing aluminum by atomic layer deposition after annealing the deposited titanium; and

annealing the deposited aluminum using oxygen to form the first layer into a layer of titanium aluminum oxide.

12. The method of claim 7 , wherein forming a first layer of at least one of titanium or aluminum and annealing the first layer includes:

depositing aluminum by atomic layer deposition;

annealing the deposited aluminum using oxygen;

depositing titanium by atomic layer deposition after annealing the deposited aluminum; and

annealing the deposited titanium using oxygen to form the first layer into a layer of titanium aluminum oxide.

13. The method of claim 7 , wherein forming a dielectric layer includes forming a nanolaminate of titanium oxide and the titanium aluminum oxide film.

14. The method of claim 7 , wherein the method is a method of forming an integrated circuit and forming the dielectric layer includes forming the dielectric layer as a gate insulator in a transistor in the integrated circuit.

15. The method of claim 7 , wherein forming the dielectric layer includes forming the dielectric layer to contact a substrate on which it is disposed substantially by a combination of titanium and aluminum atoms.

16. A method comprising:

forming a dielectric layer containing a titanium aluminum oxide film in an integrated circuit, the titanium aluminum oxide being a bimetal oxide (TiAlO x ), the forming of the titanium aluminum oxide film including:

forming a first layer of titanium aluminum oxide by atomic layer deposition;

annealing the first layer using atomic oxygen;

forming a second layer of titanium aluminum oxide onto and contacting the first layer by atomic layer deposition, after annealing the first layer, to form contiguous layers of titanium aluminum oxide; and

controlling the forming of the layers of titanium aluminum oxide such that the layers of titanium aluminum oxide have more titanium than aluminum.

17. The method of claim 16 , wherein forming a first layer includes forming the first layer as a monolayer of titanium aluminum oxide.

18. The method of claim 16 , wherein forming a first layer of titanium aluminum oxide includes using TiI 4 as a precursor.

19. The method of claim 16 , wherein forming a second layer of titanium aluminum oxide includes using TiCl 4 as a precursor.

20. The method of claim 16 , wherein forming a first layer of titanium aluminum oxide includes using trimethyl aluminum as a precursor.

21. The method of claim 16 , wherein forming a dielectric layer includes forming a nanolaminate of titanium oxide and the titanium aluminum oxide film.

22. The method of claim 16 , wherein the method is a method of forming an integrated circuit and forming the dielectric layer includes forming the dielectric layer as a gate insulator in a transistor in the integrated circuit.

23. The method of claim 16 , wherein the method is a method of forming an integrated circuit and forming the dielectric layer includes forming the dielectric layer as a gate insulator in a CMOS transistor in the integrated circuit.

24. The method of claim 16 , wherein forming the dielectric layer includes forming the dielectric layer to contact a substrate on which it is disposed is substantially by a combination of titanium and aluminum atoms.

25. A method comprising:

forming a memory array including:

forming a dielectric layer containing a titanium aluminum oxide film in an integrated circuit, the titanium aluminum oxide being a bimetal oxide (TiAlO x ), the forming of the titanium aluminum oxide film including:

forming a first layer of at least one of titanium or aluminum by atomic layer deposition using two or more atomic layer deposition cycles;

annealing the first layer using atomic oxygen to convert the first layer to an oxide layer; and

forming a second layer, the second layer being a layer of titanium aluminum oxide, the second layer formed onto and contacting the first layer by atomic layer deposition, after annealing the first layer, to form contiguous layers of titanium aluminum oxide; and

forming an address decoder, the address decoder coupled to the memory array.

26. The method of claim 25 , wherein forming a first layer includes forming the first layer as a layer of titanium and aluminum.

27. The method of claim 25 , wherein forming a second layer of titanium aluminum oxide includes:

depositing at least one of titanium or aluminum on the first layer by atomic layer deposition; and

annealing the deposited at least one of titanium or aluminum using atomic oxygen.

28. The method of claim 25 , wherein forming a first layer of at least one of titanium or aluminum and annealing the first layer includes:

depositing titanium by atomic layer deposition;

annealing the deposited titanium using atomic oxygen;

depositing aluminum by atomic layer deposition after annealing the deposited titanium; and

annealing the deposited aluminum using atomic oxygen to form the first layer into a layer of titanium aluminum oxide.

29. The method of claim 25 , wherein forming a first layer of at least one of titanium or aluminum and annealing the first layer includes:

depositing aluminum by atomic layer deposition;

annealing the deposited aluminum using atomic oxygen;

depositing titanium by atomic layer deposition after annealing the deposited aluminum; and

annealing the deposited titanium using atomic oxygen to form the first layer into a layer of titanium aluminum oxide.

30. The method of claim 25 , wherein the method is a method of forming a memory device and forming the dielectric layer includes forming the dielectric layer as a gate insulator of a transistor in the memory array.

31. The method of claim 25 , wherein the method is a method of forming a flash memory device and forming the dielectric layer includes forming the dielectric layer as an inter-gate insulator between and contacting a floating gate and a control gate of a transistor in the flash memory device.

32. A method comprising:

forming a memory array including:

forming a dielectric layer containing a titanium aluminum oxide film in an integrated circuit, the titanium aluminum oxide being a bimetal oxide (TiAlO x ), the forming of the titanium aluminum oxide film including:

forming a first layer of titanium aluminum oxide by atomic layer deposition;

annealing the first layer using oxygen;

forming a second layer of titanium aluminum oxide onto and contacting the first layer by atomic layer deposition, after annealing the first layer, to form contiguous layers of titanium aluminum oxide; and

controlling the forming of the layers of titanium aluminum oxide such that the layers of titanium aluminum oxide have more titanium than aluminum; and

forming an address decoder coupled to the memory array.

33. The method of claim 32 , wherein annealing the first layer using oxygen includes annealing the first layer substantially using atomic oxygen.

34. The method of claim 32 , wherein forming a first layer of titanium aluminum oxide includes using a number of cycles to form at most four monolayers of titanium aluminum oxide as the first layer.

35. The method of claim 32 , wherein forming the dielectric layer includes forming a silicon oxide interface layer between and contacting the dielectric layer and a substrate on which the dielectric is disposed such that the silicon oxide interface layer is at most two monolayers thick.

36. The method of claim 32 , wherein forming a dielectric layer includes forming the dielectric layer substantially without a silicon oxide interface layer between and contacting the dielectric layer and a substrate on which the dielectric is disposed.

37. The method of claim 32 , wherein forming the dielectric layer includes forming the dielectric layer substantially as the titanium aluminum oxide film.

38. The method of claim 32 , wherein forming the dielectric layer includes forming the dielectric layer such that contact to a substrate on which the dielectric layer is disposed is substantially provided by titanium atoms, aluminum atoms, or a combination of titanium and aluminum atoms.

39. The method of claim 32 , wherein the method is a method of forming a memory device and forming the dielectric layer includes forming the dielectric layer as a gate insulator of a transistor in the memory array.

40. The method of claim 32 , wherein the method is a method of forming a flash memory device and forming the dielectric layer includes forming the dielectric layer as an inter-gate insulator between and contacting a floating gate and a control gate of a transistor in the flash memory device.

41. The method of claim 32 , wherein the method is a method of forming a memory device including forming the dielectric layer as a dielectric of a capacitor in the memory device.

42. A method comprising:

providing a controller;

coupling an integrated circuit to the controller, wherein the integrated circuit includes a dielectric layer containing a titanium aluminum oxide film formed by atomic layer deposition, the titanium aluminum oxide being a bimetal oxide (TiAlO x ), wherein forming the titanium aluminum oxide film includes:

forming a first layer of titanium aluminum oxide by atomic layer deposition using two or more atomic layer deposition cycles;

annealing the first layer using atomic oxygen;

forming a second layer of titanium aluminum oxide onto and contacting the first layer by atomic layer deposition, after annealing the first layer, to form contiguous layers of titanium aluminum oxide; and

controlling the forming of the layers of titanium aluminum oxide such that the layers of titanium aluminum oxide have more titanium than aluminum.

43. The method of claim 42 , wherein coupling an integrated circuit to the controller includes coupling a memory device formed as the integrated circuit having the dielectric layer containing the titanium aluminum oxide film.

44. The method of claim 42 , wherein providing a controller includes providing a processor.

45. The method of claim 42 , wherein coupling an integrated circuit to the controller includes coupling a mixed signal integrated circuit formed as the integrated circuit having the dielectric layer containing the titanium aluminum oxide film.

46. The method of claim 42 , wherein forming a first layer of titanium aluminum oxide includes using a titanium halide precursor.

47. The method of claim 42 , wherein forming a dielectric layer includes forming a silicon oxide interface layer between the dielectric layer and a substrate on which the dielectric layer is formed such that the silicon oxide interface layer is at most two monolayers thick.

48. The method of claim 42 , wherein forming a dielectric layer includes forming the dielectric layer substantially without a silicon oxide interface layer between the dielectric layer and a substrate on which the dielectric layer is formed.

49. The method of claim 42 , wherein forming a dielectric layer includes forming the dielectric layer to contact a substrate on which the dielectric layer is formed substantially by titanium atoms, aluminum atoms, or a combination of titanium and aluminum atoms.

50. The method of claim 42 , wherein the method is a method of forming an information handling system.

51. The method of claim 42 , wherein forming an information handling system includes forming a computer.

52. The method of claim 42 , wherein forming an information handling system includes forming a wireless communication system.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2004
From: AHN, KIE Y.; FORBES, LEONARD
To: MICRON TECHNOLOGY INC.
Reel/Frame 015765/0364 →
Continuity (1)
Related Publication 20060043504A1 · Mar 2, 2006