Integrated circuit manufacturing method using hard mask
An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask layer over the low-K dielectric layer; forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer; applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer; depositing an interconnect metal in the via opening; and chemical-mechanical polishing the interconnect metal and the ultra low-K dielectric layer.
1. An integrated circuit processing system comprising:
providing a substrate having an integrated circuit;
forming an interconnect layer over the integrated circuit;
applying a low-K dielectric layer over the interconnect layer;
applying a hard mask layer over the low-K dielectric layer;
forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer;
applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer;
depositing an interconnect metal in the via opening; and
chemical-mechanical polishing the interconnect metal and the low-K dielectric layer.
2. The system as claimed in claim 1 further comprising forming a diffusion barrier layer between the low-K dielectric layer and the interconnect metal.
3. The system as claimed in claim 1 wherein applying the first fluid and the second fluid includes depositing the second fluid over the first fluid.
4. The system as claimed in claim 1 further comprising forming a cap layer over the interconnect layer.
5. The system as claimed in claim 1 wherein applying the first fluid for protecting an interconnect from the second fluid.
6. An integrated circuit processing system comprising:
providing a substrate having an integrated circuit;
forming an interconnect layer over the integrated circuit including providing an interconnect within the interconnect layer;
applying a low-K dielectric layer over the interconnect layer;
applying a hard mask layer over the low-K dielectric layer includes protecting the low-K dielectric layer from the photoresist;
forming a via opening through the hard mask layer and the low-K dielectric layer to the interconnect layer includes forming an opening in a cap layer;
applying a first fluid and a second fluid in the via opening for removing an overhang of the hard mask layer includes protecting the cap layer from the second fluid;
depositing interconnect metal in the via opening to form a connection to the interconnect within the interconnect layer; and
chemical-mechanical polishing the interconnect metal and the low-K dielectric layer.
7. The system as claimed in claim 6 further comprising forming a diffusion barrier layer between the low-K dielectric layer and the interconnect metal in which the diffusion barrier layer forms a barrier to the interconnect metal.
8. The system as claimed in claim 6 wherein applying the first fluid and the second fluid includes depositing the second fluid over the first fluid in which the first fluid includes de-ionized water, a buffer solution, a solvent, or a gel.
9. The system as claimed in claim 6 further comprising forming a cap layer over the interconnect layer in which the cap layer is silicon nitride.
10. The system as claimed in claim 6 wherein applying the first fluid for protecting an interconnect from the second fluid includes applying a first fluid for slowing the diffusion of the second fluid.