Three dimensional flash cell
A floating gate memory cell includes isolation regions between adjacent cells, and a staggered pattern of columns of cells. Word lines are formed parallel to control gate structures.
1. An array of memory cells, comprising:
a plurality of rows of memory cell pillars each pillar having a pair of memory cells formed thereon, each memory cell pillar isolated from an adjacent memory cell pillar by an isolation region within its row;
wherein each memory cell pillar comprises:
a substrate;
two source regions and one drain region, the drain region vertically spaced apart from the source regions to define two separate channel regions;
a floating gate located adjacent each channel region, each floating gate extending substantially vertically; and
a control gate located adjacent to each floating gate;
wherein every memory cell coupled to a first side of a word line is within one row of memory cells and every memory cell coupled to a second side of the word line is within an adjacent row of memory cells;
wherein the memory cells of the one row of memory cells are coupled to alternating bit lines and the memory cells of the adjacent row of memory cells are coupled to alternating bit lines; and
wherein the alternating bit lines coupled to the memory cells of the one row of memory cells are different from the alternating bit lines coupled to the memory cells of the adjacent row of memory cells.
2. The array of memory cells of claim 1 wherein the source regions of each pillar are on opposite sides of the pillar.
3. The array of memory cells of claim 1 , wherein the word line controls the memory cells of the one row of memory cells and the memory cells of the adjacent row of memory cells.
4. The array of memory cells of claim 1 and further including an oxide-nitride-oxide layer between each floating gate and its respective control gate.
5. The array of memory cells of claim 1 and further including an oxide layer between each floating gate and its respective control gate.
6. The array of memory cells of claim 1 and further including:
a dielectric layer formed over the memory array; and
a metal contact formed through the dielectric layer such that adjacent drain regions of the array are coupled by the metal contact.
7. The array of memory cells of claim 1 , wherein the memory cells of each pair of memory cells formed on each pillar are formed on opposite sides of that pillar.
8. The array of memory cells of claim 1 , wherein the source regions are substantially parallel to the isolation region.
9. An array of memory cells, comprising:
a plurality of rows of memory cell pillars each pillar having a pair of memory cells formed thereon, each memory cell pillar isolated from an adjacent memory cell pillar by an isolation region within its row;
wherein each memory cell pillar comprises:
a substrate;
two source regions and one drain region, the drain region vertically spaced apart from the source regions to define two separate channel regions;
a floating gate located adjacent each channel region, each floating gate extending substantially vertically; and
a control gate located adjacent to each floating gate;
wherein every memory cell coupled to a first side of a word line is within one row of memory cells and every memory cell coupled to a second side of the word line is within an adjacent row of memory cells;
wherein the memory cells of the one row of memory cells are coupled to alternating bit lines and the memory cells of the adjacent row of memory cells are coupled to alternating bit lines;
wherein the alternating bit lines coupled to the memory cells of the one row of memory cells are different from the alternating bit lines coupled to the memory cells of the adjacent row of memory cells; and
wherein each bit line is coupled to the drain region of each memory cell pillar of a column of memory cell pillars, the memory cell pillars of the column belonging to alternating rows of memory cell pillars.
10. The array of memory cells of claim 9 , wherein each bit line is coupled to a drain region of a pillar by a contact.
11. The array of memory cells of claim 9 , further comprising:
a dielectric layer formed over the memory array;
wherein each bit line is coupled to a drain region of a pillar by a contact formed through the dielectric layer.
12. The array of memory cells of claim 9 , wherein the source regions of each pillar are on opposite sides of the pillar.
13. The array of memory cells of claim 9 , further comprising:
a first dielectric interposed between the substrate and each floating gate; and
a second dielectric interposed between each floating gate and its respective control gate.
14. An array of memory cells, comprising:
a plurality of rows of memory cell pillars each pillar having a pair of memory cells formed thereon, each memory cell pillar isolated from an adjacent memory cell pillar by an isolation region within its row;
wherein each memory cell pillar comprises:
a substrate;
two source regions and one drain region, the drain region vertically spaced apart from the source regions to define two separate channel regions;
a floating gate located adjacent each channel region, each floating gate extending substantially vertically; and
a control gate located adjacent to each floating gate;
a plurality of bit lines, each bit line of the plurality of bit lines coupled to pairs of memory cells formed on pillars within alternating rows of pillars;
wherein every memory cell coupled to a first side of a word line is within one row of memory cells and every memory cell coupled to a second side of the word line is within an adjacent row of memory cells;
wherein the memory cells of the one row of memory cells are coupled to alternating bit lines of the plurality of bit lines and the memory cells of the adjacent row of memory cells are coupled to alternating bit lines of the plurality of bit lines;
wherein the alternating bit lines coupled to the memory cells of the one row of memory cells are different from the alternating bit lines coupled to the memory cells of the adjacent row of memory cells; and
wherein respective memory cells of each pair of memory cells formed on a pillar are coupled to adjacent word lines.
15. The array of memory cells of claim 14 , further comprising:
a dielectric layer formed over the memory array;
wherein each of the plurality of bit lines is coupled to a drain region of a pillar by a contact formed through the dielectric layer.