Junction field effect dynamic random access memory cell and content addressable memory cell

1. A semiconductor device, comprising:

a memory cell including

a first junction field effect transistor (JFET) having a first controllable impedance path coupled between a first bit line and a data storing node, the first JFET includes a first control gate terminal coupled to a first word line; and

a capacitor having a first terminal coupled to the data storing node and a second terminal coupled to a first potential.

2. The semiconductor device of claim 1 , wherein the memory cell further includes:

a first stack including a second JFET having a second controllable impedance path and a third JFET having a third controllable impedance path, the second and third controllable impedance paths coupled in series between a second potential and a second bit line and the second JFET includes a second control gate terminal coupled to the data storing node and the third JFET includes a third control gate terminal coupled to a second word line.

3. The semiconductor device of claim 2 , wherein:

the first JFET, the second JFET, and the third JFET are p-channel JFETs.

4. The semiconductor device of claim 2 , wherein:

the second JFET has a source terminal coupled to the second potential and a drain terminal coupled to a source terminal of the third JFET and the third JFET has a drain terminal coupled to the second bit line.

5. The semiconductor device of claim 2 , wherein:

the third JFET has a source terminal coupled to the second potential and a drain terminal coupled to a source terminal of the second JFET and the second JFET has a drain terminal coupled to the second bit line.

6. The semiconductor device of claim 2 , wherein:

the first potential is higher than the second potential.

7. The semiconductor device of claim 6 , wherein:

the first potential is a boosted voltage; and

the second potential is a power supply potential.

8. The semiconductor device of claim 2 , wherein:

the first potential is a ground potential; and

the second potential is a power supply potential.

9. The semiconductor device of claim 1 wherein the memory cell is a dynamic random access memory (DRAM) cell.

10. The semiconductor device of claim 9 wherein the memory cell requires a periodic refresh.

11. The semiconductor device of claim 1 , wherein the first JFET includes a second gate terminal coupled to the word line.

12. A semiconductor device, comprising:

a content addressable memory (CAM) cell including

a first junction field effect transistor (JFET) having a first controllable impedance path coupled between a first bit line and

a first data storing node, the first JFET includes a first JFET control gate coupled to a word line;

a first capacitor having a first terminal and a second terminal, and the first terminal being coupled to the first data storing node; and

a first stack including a second JFET having a second controllable impedance path and a third JFET having a third controllable impedance path, the second and third controllable impedance paths coupled in series between a first potential and a match line and the second JFET includes a second control gate terminal coupled to the first data storing node and the third JFET includes a third control gate terminal coupled to receive first compare data.

13. The semiconductor device of claim 12 , wherein the first JFET includes a second first JFET control gate coupled to the word line.

14. The semiconductor device of claim 12 , wherein the second JFET is a depletion mode JFET.

15. The semiconductor device of claim 12 , wherein:

the first, second, and third JFETs are p-channel JFETs.

16. The semiconductor device of claim 12 , wherein:

the first potential is a power supply potential.

17. The semiconductor device of claim 16 , wherein:

the second terminal of the capacitor is coupled to a boosted power supply potential greater than the power supply potential.

18. The semiconductor device of claim 12 , wherein:

the third JFET has a source coupled to the match line and a drain coupled to a source of the second JFET and the second JFET includes a drain coupled to the first potential and the first potential is a ground potential.

19. The semiconductor device of claim 12 , wherein:

the third JFET has a source coupled to the first potential and a drain coupled to a source of the second JFET and the second JFET includes a drain coupled to the match line and the first potential is a power supply potential.

20. The semiconductor device of claim 12 , wherein:

the second JFET has a source coupled to the first potential and a drain coupled to a source of the third JFET and the third JFET includes a drain coupled to the match line and the first potential is a power supply potential.

21. The semiconductor device of claim 12 , wherein the CAM cell further includes:

a fourth JFET having a fourth controllable impedance path coupled between a second bit line and a second data storing node, the fourth JFET includes a first control gate terminal coupled to the word line;

a second capacitor having a first terminal and a second terminal and the first terminal of the second capacitor being coupled to the second data storing node; and

a second stack including a fifth JFET having a fifth controllable impedance path and a sixth JFET having a sixth controllable impedance path, the fifth and sixth controllable impedance paths coupled in series between the first potential and the match line and the fifth JFET includes a fifth control gate terminal coupled to the second data storing node and the sixth JFET includes a sixth control gate terminal coupled to receive second compare data.

22. The semiconductor device of claim 21 , wherein:

the second compare data is complementary to the first compare data.

23. The semiconductor device of claim 21 , wherein:

the CAM cell is a ternary CAM cell.

24. The semiconductor device of claim 12 , wherein:

the first data storing node requires periodic refresh.

25. A semiconductor device, comprising:

a dynamic random access memory (DRAM) cell including

a data storing portion including a first p-channel junction field effect transistor (JFET) and coupled to receive a write bit line and a write word line as inputs for storing a data logic value on a data storing node coupled to the first JFET and a capacitor; and

a data read portion including a second p-channel JFET and coupled to receive the data logic value from the data storing node and a read word line as inputs and providing read data on a read word line as an output wherein the read data has the data logic value.

26. A semiconductor device, comprising:

a content addressable memory cell (CAM) including

a first data storing portion including a first junction field effect transistor (JFET) and coupled to receive a first bit line and a word line as inputs for storing a first data logic value on a first data storing node coupled to the first JFET and a first capacitor; and

a first data compare portion including a second JFET and coupled to receive the first data logic value from the first data storing node and a first compare data as inputs and providing a compare result on a match line, the compare result based on the first data logic value and the first compare data.

27. The semiconductor device of claim 26 , wherein the CAM cell further includes:

a second data storing portion including a third junction field effect transistor (JFET) and coupled to receive a second bit line and the word line as inputs for storing a second data logic value on a second data storing node coupled to the third JFET and a second capacitor; and

a second data compare portion including a fourth JFET and coupled to receive the second data logic value from the second data storing node and a second compare data as inputs and providing the compare result on the match line, the compare result based on the second data logic value and the second compare data.