Lattice-mismatched semiconductor structures on insulators
Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the underlying substrates to produce alternative active-area regions disposed over the insulator and substantially exhausted of misfit and threading dislocations.
1. A semiconductor device structure comprising:
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over the substrate, the patterned insulator layer defining a first opening and a second opening exposing portions of the base insulator layer;
a first active-area region formed in the first opening, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 10 5 cm −2 and disposed over and in contact with the base insulator layer;
a second active-area region formed in the second opening, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 10 5 cm −2 and disposed over and in contact with the base insulator layer;
a p-type metal-oxide-semiconductor (PMOS) transistor disposed over and including at least a portion of the first active-area region, the PMOS transistor including:
a first gate dielectric region disposed over the first active-area region,
a first gate disposed over the first gate dielectric region, the first gate comprising a first conducting layer,
a first source and a first drain regions formed in the first active-area region proximate the first gate dielectric region, the first source and first drain region including p-type dopants; and
an n-type metal-oxide-semiconductor (NMOS) transistor disposed over and including at least a portion of the second active-area region, the NMOS transistor including:
a second gate dielectric region disposed over the second active-area region,
a second gate disposed over the second gate dielectric region, the second gate comprising a second conducting layer,
a second source and a second drain regions formed in the second active-area region proximate the second gate dielectric region, the second source and second drain including n-type dopants,
wherein both the first active-area material and the second active-area material are different from the first crystalline semiconductor material, and the first active-area material is different from the second active-area material.
2. The structure of claim 1 further comprising a strained semiconductor layer disposed over at least one of the first active-area material or the second active-area material.
3. The structure of claim 1 wherein the first active area-material and the second active-area material are substantially free of misfit dislocations.
4. The structure of claim 1 wherein the first active-area material and the second active-area material are substantially free of threading dislocations.
5. The structure of claim 1 wherein the first active-area material is substantially relaxed to its equilibrium lattice constant and the second active-area material is substantially relaxed to its equilibrium lattice constant.
6. The structure of claim 1 wherein the first crystalline semiconductor material comprises silicon, the first active-area material comprises germanium, and the second active-area material comprises a III-V compound.
7. The structure of claim 6 wherein the first crystalline semiconductor material consists essentially of silicon, the first active-area material consists essentially of germanium, and the second active-area material consists essentially of the III-V compound.
8. The structure of claim 1 wherein, during operation, an off-state current of the PMOS transistor and an off-state current of the NMOS transistor are both less than about 10 −8 A/μm.
9. The structure of claim 1 wherein a lattice mismatch between the first active-area material and the first crystalline semiconductor material and a lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 4%.
10. The structure of claim 9 wherein the lattice mismatch between the first active-area material and the first crystalline semiconductor material and the lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 8%.
11. The structure of claim 1 further comprising a strained semiconductor layer disposed between the first active-area material and the first gate dielectric region.
12. The structure of claim 1 further comprising a strained semiconductor layer disposed between the second active-area material and the second gate dielectric region.
13. The structure of claim 1 wherein a dislocation pile-up density of the first active-area material and a dislocation pile-up density of the second active-area material are both less than about 1/cm.
14. The structure of claim 1 wherein the base insulator layer consists essentially of at least one of silicon dioxide or silicon nitride.
15. A semiconductor structure comprising:
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over and in direct contact with the base insulator layer, the patterned insulator layer defining a first opening and a second opening;
a first active-area region formed in the first opening and in contact with the substrate, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 10 5 cm −2 ; and
a second active-area region formed in the second opening and in contact with the substrate, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 10 5 cm −2 ,
wherein the first active-area material is different from the second active-area material, the first active-area material is disposed over and in contact with the base insulator layer, and the second active-area material is disposed over and in contact with the base insulator layer, the first crystalline semiconductor material comprises silicon, the first active-area material comprises germanium, and the second active-area material comprises a III-V compound.
16. The semiconductor structure of claim 15 further comprising:
a p-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the first active-area region; and
an n-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the second active-area region.
17. The structure of claim 16 wherein, during operation, an off-state current of the p-type metal-oxide-semiconductor transistor and an off-state current of the n-type metal-oxide-semiconductor transistor are both less than about 10 −8 A/μm.
18. The structure of claim 15 wherein the first active area-material and the second active-area material are substantially free of misfit dislocations.
19. The structure of claim 15 wherein the first active-area material and the second active-area material are substantially free of threading dislocations.
20. The structure of claim 15 wherein the first active-area material is substantially relaxed to its equilibrium lattice constant and the second active-area material is substantially relaxed to its equilibrium lattice constant.
21. The structure of claim 15 wherein the first crystalline semiconductor material consists essentially of silicon, the first active-area material consists essentially of germanium, and the second active-area material consists essentially of the III-V compound.
22. The structure of claim 15 wherein a dislocation pile-up density of the first active-area material and a dislocation pile-up density of the second active-area material are both less than about 1/cm.
23. The structure of claim 15 wherein the base insulator layer consists essentially of at least one of silicon dioxide or silicon nitride.
24. The structure of claim 15 , further comprising a strained semiconductor layer disposed over the first active-area material.
25. The structure of claim 24 further comprising a second strained semiconductor layer disposed over the second active-area material.
26. The structure of claim 15 further comprising a strained semiconductor layer disposed over the second active-area material.
27. A semiconductor structure comprising:
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over and in direct contact with the base insulator layer, the patterned insulator layer defining a first opening and a second opening;
a first active-area region formed in the first opening and in contact with the substrate, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 10 5 cm −2 ;
a second active-area region formed in the second opening and in contact with the substrate, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 10 5 cm −2 ; and
a strained semiconductor layer disposed over the first active-area material,
wherein the first active-area material is different from the second active-area material, the first active-area material is disposed over and in contact with the base insulator layer, and the second active-area material is disposed over and in contact with the base insulator layer.
28. The semiconductor structure of claim 27 wherein both the first active-area material and the second active-area material are different from the first crystalline semiconductor material.
29. The structure of claim 27 wherein a lattice mismatch between the first active-area material and the first crystalline semiconductor material and a lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 4%.
30. The structure of claim 29 wherein the lattice mismatch between the first active-area material and the first crystalline semiconductor material and the lattice mismatch between the second active-area material and the first crystalline semiconductor material both exceed approximately 8%.
31. The structure of claim 27 further comprising a second strained semiconductor layer disposed over the second active-area material.
32. The structure of claim 27 further comprising:
a p-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the first active-area region; and
an n-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the second active-area region.
33. The structure of claim 32 wherein, during operation, an off-state current of the p-type metal-oxide-semiconductor transistor and an off-state current of the n-type metal-oxide-semiconductor transistor are both less than about 10 −8 A/μm.
34. The structure of claim 32 wherein the first active area-material and the second active-area material are substantially free of misfit dislocations.
35. The structure of claim 32 wherein the first active-area material and the second active-area material are substantially free of threading dislocations.
36. The structure of claim 32 wherein the first active-area material is substantially relaxed to its equilibrium lattice constant and the second active-area material is substantially relaxed to its equilibrium lattice constant.
37. The structure of claim 32 wherein a dislocation pile-up density of the first active-area material and a dislocation pile-up density of the second active-area material are both less than about 1/cm.
38. The structure of claim 32 wherein the base insulator layer consists essentially of at least one of silicon dioxide or silicon nitride.
39. A semiconductor structure comprising;
a substrate comprising a base insulator layer disposed over a base semiconductor layer comprising a first crystalline semiconductor material;
a patterned insulator layer disposed over and in direct contact with the base insulator layer, the patterned insulator layer defining a first opening and a second opening;
a first active-area region formed in the first opening and in contact with the substrate, the first active-area region comprising a first active-area material having a threading dislocation density less than approximately 10 5 cm −2 ;
a second active-area region formed in the second opening and in contact with the substrate, the second active-area region comprising a second active-area material having a threading dislocation density less than approximately 10 5 cm −2 ; and
a strained semiconductor layer disposed over the second active-area material,
wherein the first active-area material is different from the second active-area material, the first active-area material is disposed over and in contact with the base insulator layer, and the second active-area material is disposed over and in contact with the base insulator layer.
40. The structure of claim 39 further comprising:
a p-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the first active-area region; and
an n-type metal-oxide-semiconductor transistor disposed over and including at least a portion of the second active-area region.
41. The structure of claim 40 wherein, during operation, an off-state current of the p-type metal-oxide-semiconductor transistor and an off-state current of the n-type metal-oxide-semiconductor transistor are both less than about 10 −8 A/μm.