Power semiconductor devices and methods of manufacture
Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.
1. A semiconductor device comprising:
a drift region of a first conductivity type;
a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;
an active trench extending into the drift region deeper than the well region, and having its sidewalls and bottom lined with dielectric material and substantially filled with a gate conductive layer;
source regions having the first conductivity type formed in the well region adjacent the active trench;
a body trench extending deeper than the well region and formed adjacent the well and it's source region, the body trench being substantially filled with conductive material; and
a layer of second concentration of the second conductivity type substantially surrounding the body trench;
wherein the active trench further includes a first shield electrode made of conductive material formed under the gate conductive layer, the shield electrode being insulated from the gate conductive layer and the trench sidewalls and bottom by a layer of dielectric material.
2. The semiconductor device of claim 1 wherein the first shield electrode inside the active trench is configured to be electrically biased to a desired potential.
3. The semiconductor device of claim 1 wherein the first shield electrode and the source regions are electrically coupled to substantially the same potential.
4. The semiconductor device of claim 1 wherein the active trench further comprises a second shield electrode made of conductive material and disposed below the first shield electrode.
5. The semiconductor device of claim 4 wherein the first and second shield electrodes vary in size.
6. The semiconductor device of claim 4 wherein the first and second shield conductive layers can be independently biased.
7. A semiconductor device comprising:
a drift region of a first conductivity type;
a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;
an active trench extending into the drift region deeper than the well region, and having its sidewalls and bottom lined with dielectric material and substantially filled with a gate conductive layer;
source regions having the first conductivity type formed in the well region adjacent the active trench;
a body trench extending deeper than the well region and formed adjacent the well and it's source region, the body trench being substantially filled with conductive material; and
a layer of second concentration of the second conductivity type substantially surrounding the body trench;
a charge control trench extending into the substrate and substantially filled with material to allow for vertical charge control in the substrate;
wherein inside the charge control trench is disposed a plurality of conductive layers stacked vertically and separated from each other and from the trench sidewalls by dielectric material.
8. The semiconductor device of claim 7 wherein the plurality of conductive layers inside the charge control trench are electrically biased to provide vertical charge balancing in the substrate.
9. The semiconductor device of claim 8 wherein the plurality of conductive layers inside the charge control trench are configured to be independently biased.
10. The semiconductor device of claim 7 wherein sizes of the plurality of conductive layers inside the charge control trench vary.
11. The semiconductor device of claim 10 wherein the size of a first conductive layer deeper inside the charge control trench is smaller than the size of a second conductive layer that is disposed above the first conductive layer.