Integrated capacitors in package-level structures, processes of making same, and systems containing same
An article includes a top electrode that is embedded in a solder mask. An article includes a top electrode that is on a core structure. A process of forming the top electrode includes reducing the solder mask thickness and forming the top electrode on the reduced-thickness solder mask. A process of forming the top electrode includes forming the top electrode over a high-K dielectric that is in a patterned portion of the core structure.
1. A process comprising:
forming a first through-hole in a core layer, wherein the core layer includes a first side and a second side;
forming a dielectric layer in the first through-hole;
forming a bottom electrode on the dielectric layer and below the core layer second side;
forming a top electrode on the dielectric layer and above the core layer, wherein forming one of the top electrode and the bottom electrode includes completing the plated through-hole;
forming a second through-hole in the core layer;
forming a plated through-hole from the second through-hole; and
coupling the core layer with a die.
2. The process of claim 1 , wherein coupling includes coupling a capacitor solder bump on the die to the top electrode, and coupling a power solder bump or a signal solder bump on the die to the plated through-hole.
3. The process of claim 1 , wherein forming a dielectric layer includes forming the dielectric layer through a stencil that is disposed above the core layer.
4. A process comprising:
forming a solder mask upon a substrate;
first patterning the solder mask to expose a bottom electrode;
forming a dielectric film upon the bottom electrode, wherein the dielectric fun and the solder mask share coplanar surfaces;
second patterning the solder mask to expose at least a first bond finger pad and a die land; and
plating a top electrode above the dielectric film.
5. The process of claim 4 , further including locating a die at a die land that is exposed during second patterning.
6. The process of claim 4 , further including:
locating a die at a die land that is exposed during second patterning; and
first wire-bonding the die by coupling the die to the top electrode.
7. The process of claim 4 , further including:
locating a die at a die land that is exposed during second patterning;
first wire-bonding the die by coupling the die to one of a power ring and a ground ring; and
second wire-bonding the die by coupling the die to a bond finger upper.
8. The process of claim 1 , wherein coupling the core layer with a die includes flip-chip coupling the die to the core layer.
9. The process of claim 1 , wherein coupling the core layer with a die includes flip-chip coupling the die to the core layer, the process further including filling an underfill material between the flip-chip and the core layer.
10. A process comprising:
forming a first through-hole in a core layer, wherein the core layer includes a first side and a second side;
forming a dielectric layer in the first through-hole through a stencil that is disposed above the core layer;
forming a bottom electrode on the dielectric layer and below the core layer second side;
forming a top electrode on the dielectric layer and above the core layer, wherein forming one of the top electrode and the bottom electrode includes completing the plated through-hole;
forming a second through-hole in the core layer;
forming a plated through-hole from the second through-hole; and
coupling the core layer with a die, wherein coupling includes coupling a capacitor solder bump on the die to the top electrode, and coupling a power solder bump or a signal solder bump on the die to the plated through-hole.
11. A process comprising:
forming a first through-hole in a core layer, wherein the core layer includes a first side and a second side;
forming a dielectric layer in the first through-hole through a stencil that is disposed above the core layer;
forming a bottom electrode on the dielectric layer and below the core layer second side;
forming a top electrode on the dielectric layer and above the core layer;
forming a second through-hole in the core layer;
forming a plated through-hole from the second through-hole; and
coupling the core layer with a die, wherein coupling includes coupling a capacitor solder bump on the die to the top electrode, and coupling a power solder bump or a signal solder bump on the die to the plated through-hole before coupling, the process further including:
covering the first side with a solder mask layer;
patterning the solder mask layer to expose at least a portion of the top electrode and at least a portion of the plated through-hole.
12. A process comprising:
forming a solder mask upon a substrate;
first patterning the solder mask to expose a bottom electrode;
forming a dielectric film upon the bottom electrode, wherein the dielectric film and the solder mask share coplanar surfaces;
second patterning the solder mask to expose at least a first bond finger pad and a die land;
plating a top electrode above the dielectric film;
locating a die at a die land that is exposed during second patterning;
first wire-bonding the die by coupling the die to the top electrode; and
second wire-bonding the die by coupling the die to a bond finger upper.
13. The process of claim 12 , wherein first wirebonding includes coupling the die to a power ring in the substrate.
14. The process of claim 12 , wherein first wirebonding includes coupling the die to a power ring in the substrate, and wherein second wire-bonding includes coupling the die to a ground ring in the substrate.
15. A process comprising:
forming a first through-hole in a core layer, wherein the core layer includes a first side and a second side;
forming a dielectric layer in the first through-hole;
forming a bottom electrode on the dielectric layer and below the core layer second side;
forming a top electrode on the dielectric layer and above the core layer;
forming a second through-hole in the core layer;
forming a plated through-hole from the second through-hole; and
coupling the core layer with a die, and before coupling, the process further including;
covering the first side with a solder mask layer;
patterning the solder mask layer to expose at least a portion of the top electrode and at least a portion of the plated through-hole.
16. The process of claim 15 , wherein coupling includes coupling a capacitor solder bump on the die to the top electrode, and coupling a power solder bump or a signal solder bump on the die to the plated through-hole.
17. The process of claim 15 , wherein forming a dielectric layer includes forming the dielectric layer through a stencil that is disposed above the core layer.
18. The process of claim 15 , wherein coupling the core layer with a die includes flip-chip coupling the die to the core layer.
19. The process of claim 15 , wherein coupling the core layer with a die includes flip-chip coupling the die to the core layer, the process further including filling an underfill material between the flip-chip and the core layer.