IP Library › Granted Patent US 7,682,879
Granted Patent B2
US 7,682,879 · App. 11/460,503 · Granted Mar 23, 2010

Edge coating a microelectronic device

Assignee: Seagate Technology LLC
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Quick Facts
Patent No.
US 7,682,879
App. No.
11/460,503
Granted
Mar 23, 2010
Kind
B2
Abstract

A microelectronic device includes a die having an active surface and a non-active surface. To assemble the microelectronic device, the active surface of the die is placed on a substrate. A first material is dispensed between the active surface of the die and the substrate. A second material is dispensed on at least a portion of the non-active surface of the die. The second material is different than the first material and the first material and the second material are simultaneously cured.

Claims (37)

1. A method of assembling a microelectronic device comprising:

providing a die having an active surface, an opposing non-active surface substantially parallel with the active surface and a plurality of sidewalls positioned about a perimeter of the die connecting the active and the non-active surfaces, the plurality of sidewalls intersect with the non-active surface to form non-active side edges;

placing the active surface of the die on a substrate;

dispensing a first material at least between the active surface of the die and the substrate, the first material having adhesive properties including a first resin and a non-conductive first filler;

dispensing a second material on at least a portion of the non-active surface of the die and on at least a portion of the first material to cover the non-active side edges of the die, the second material is in contact with the first material and leaves at least a portion of the non-active surface exposed to a surrounding environment of the die, the second material having thixotropic properties including a second resin and a non-conductive second filler; and

simultaneously curing the first material and the second material.

2. The method of claim 1 , wherein placing the active surface of the die on the substrate comprises placing the active surface of the die on a flexible circuit assembly located in an enclosure of an electronic device.

3. The method of claim 2 , wherein the electronic device comprises a data storage system.

4. The method of claim 1 , wherein providing a die comprises providing a semiconductor die made of silicon.

5. The method of claim 4 , wherein providing the semiconductor die comprises providing a preamplifier integrated circuit.

6. The method of claim 1 , further comprising depositing a plurality of conductive bumps on the active surface of the die prior to placing the active surface of the die on the substrate.

7. The method of claim 6 , further comprising heating the conductive bumps after placing the active surface of the die on the substrate such that the bumps make an electrical connection with a corresponding plurality of electrical leads on the substrate.

8. A microelectronic device comprising:

a die having an active surface an opposing a non-active surface substatially parallel with the active surface and a plurality of sidewalls positioned about a perimeter of the die connecting the active and non-active surfaces and forming non-active side edges where the sidewalls meet with the non-active surface, the active surface of the die configured to be placed on a substrate;

an underfill material deposited at least between the active surface of the die and the substrate, the underfill material having adhesive properties including a first resin and a non-conductive first filler;

a second material deposited on at least a portion of the non-active surface of the die to cover the non-active side edges of the die and leave at least a portion of the non-active surface exposed to a surrounding environment of the die, the second material in contact with the non-conductive underfill material and having thixotropic properties including a second resin and a non-conductive second filler; and

wherein the underfill material and the second material are simultaneously cured.

9. The microelectronic device of claim 8 , wherein the die comprises a plurality of sidewalls positioned about a perimeter of the die and between the active and the non-active surfaces, wherein the sidewalls form non-active side edges with the non-active surface.

10. The microelectronic device of claim 8 , wherein the substrate comprises a flexible circuit assembly.

11. The microelectronic device of claim 8 , wherein the substrate is included in an enclosure of an electronic device.

12. The microelectronic device of claim 11 , wherein the electronic device comprises a data storage system.

13. The microelectronic device of claim 8 , wherein the die comprises a preamplifier integrated circuit.

14. A microelectronic device comprising:

a semiconductor die including:

a non-active surface;

an opposing active surface substantually parallel with the non-active surface and configured to be placed on a substrate;

a plurality of sidewalls positioned about a perimeter of the die and connecting the active and non-active surfaces, the plurality of sidewalls intersect with the non-active surface and the active surface to form side edges of the die;

a first material having adhesive properties including a first resin and a first filler, the first material dispensed between the active surface of the semiconductor die and the substrate;

a second material having thixotropic properties including a second resin and a second filler, the second material dispensed to coat all side edges of the semiconductor die and at least a portion of the non-active surface such that none of the edges of the die are left exposed to the surrounding environment of the die and at least a portion of the non-active surface is left exposed to the surrounding environment; and

wherein the first material and the second material are in contact and are simultaneously cured.

15. The microelectronic device of claim 14 , wherein the substrate comprises a flexible circuit assembly.

16. The microelectronic device of claim 15 , wherein the flexible circuit assembly is located in an enclosure of an electronic device.

17. The microelectronic device of claim 16 , wherein the electronic device comprises a data storage system.

18. An apparatus comprising:

a die having a non-active surface and an opposing active surface that is configured to be placed in electrical communication with a substrate;

an electrically non-conductive underfill material also operably extending outwardly from a sidewall of the die and covering an active edge of the die;

a second material operably supported by the underfill material and not contactingly engaging the substrate, the second material operably covering a non-active side edge of the die but leaving at least a portion of the non-active surface exposed to a surrounding environment of the die and leaving a least a portion of the underfill material exposed to the surrounding environment of the die.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Jul 23, 2025
From: THE BANK OF NOVA SCOTIA
To: SEAGATE TECHNOLOGY PUBLIC LIMITED COMPANY; SEAGATE TECHNOLOGY; SEAGATE TECHNOLOGY HDD HOLDINGS; I365 INC.; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL; SEAGATE HDD CAYMAN; SEAGATE TECHNOLOGY (US) HOLDINGS, INC.
Reel/Frame 072193/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS Recorded Jul 19, 2013
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT AND SECOND PRIORITY REPRESENTATIVE
To: SEAGATE TECHNOLOGY LLC; EVAULT INC. (F/K/A I365 INC.); SEAGATE TECHNOLOGY INTERNATIONAL; SEAGATE TECHNOLOGY US HOLDINGS, INC.
Reel/Frame 030833/0001 →
SECURITY AGREEMENT Recorded Mar 24, 2011
From: SEAGATE TECHNOLOGY LLC
To: THE BANK OF NOVA SCOTIA, AS ADMINISTRATIVE AGENT
Reel/Frame 026010/0350 →
RELEASE Recorded Jan 19, 2011
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: SEAGATE TECHNOLOGY HDD HOLDINGS; MAXTOR CORPORATION; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL
Reel/Frame 025662/0001 →
SECURITY AGREEMENT Recorded May 15, 2009
From: MAXTOR CORPORATION; SEAGATE TECHNOLOGY LLC; SEAGATE TECHNOLOGY INTERNATIONAL
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND FIRST PRIORITY REPRESENTATIVE; WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT AND SECOND PRIORITY REPRESENTATIVE
Reel/Frame 022757/0017 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE'S STATE PREVIOUSLY RECORDED ON REEL 018018 FRAME 0598. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT.. Recorded Aug 2, 2006
From: ECHOLS, ROBERT MICHAEL; FABRY, MICHAEL RICHARD
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 018044/0014 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2006
From: ECHOLS, ROBERT MICHAEL; FABRY, MICHAEL RICHARD
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 018018/0598 →
Continuity (2)
Provisional Application 6078647300 · Mar 28, 2006
Related Publication 20070228532A1 · Oct 4, 2007