IP Library › Granted Patent US 7,704,847
Granted Patent B2
US 7,704,847 · App. 11/419,341 · Granted Apr 27, 2010

On-chip heater and methods for fabrication thereof and use thereof

Assignee: International Business Machines Corporation
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Quick Facts
Patent No.
US 7,704,847
App. No.
11/419,341
Granted
Apr 27, 2010
Kind
B2
Abstract

An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

Claims (16)

1. A method for fabricating a semiconductor structure comprising:

forming a trench isolation region located within a semiconductor substrate; and

forming at least one heater located embedded within the trench isolation region so that an upper surface of the heater is below an upper surface of the trench isolation region.

2. The method of claim 1 wherein the forming the trench isolation region comprises forming the isolation region of a dielectric material.

3. The method of claim 1 wherein the forming the at least one heater comprises forming the at least one heater of a resistive material.

4. The method of claim 1 wherein the forming the at least one heater comprises forming the at least one heater of a resistive polysilicon material.

5. The method of claim 1 wherein the forming the at least one heater comprises forming the at least one heater located completely embedded within the trench isolation region.

6. The method of claim 1 wherein the forming the at least one heater provides that the heater has a thermal output sufficient to heat the semiconductor substrate to a temperature of at least about 200° C.

7. The method of claim 1 further comprising forming at least two contacts to the at least one heater that penetrate through the trench isolation region.

8. The method of claim 1 wherein an upper surface of the trench isolation region and an upper surface of the semiconductor substrate are coplanar.

9. A method for fabricating a semiconductor structure comprising:

forming at least one trench in a semiconductor substrate;

filling the at least one trench with an insulating material;

removing a portion of insulating material from the at least one trench, wherein a remaining portion of the insulating material is present on a base and sidewalls of the at least one trench;

forming a heater material on the remaining portion of the insulating material, wherein an upper surface of the heater material is recessed within the trench; and

filling a remainder of the at least one trench with a dielectric cap.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 19, 2006
From: CANNON, ETHAN H.; STRONG, ALVIN W.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 017651/0366 →
Continuity (1)
Related Publication 20070268736A1 · Nov 22, 2007