Method, apparatus, and system for LPC hot spot fix
View Patent ↗Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method for creating a layout from a circuit design is described. The method includes applying a first set of hot spot conditions to a global route to produce a detailed route; applying a second set of hot spot conditions to the detailed route to produce a post-detailed route; and applying a third set of hot spot conditions to the post-detailed route to produce the layout. In another aspect, a method includes providing a circuit design; applying a first hot spot filter to a global routing of the circuit design to produce a detailed route; applying a less pessimistic, second hot spot filter to the detailed route to produce a post-detailed route; and performing a rip-up and reroute of the post-detailed route to produce a final layout.
1. A method comprising:
providing, by using a computer, a circuit design having an objective;
providing, by using the computer, a first photolithography hot spot filter comprising a first set of hot spot conditions based on photolithography simulations, the first set of hot spot conditions configured to optimize the objective of the circuit design and configured to identify potential hot spots in a global route of the circuit design;
applying, by using the computer, the first hot spot filter to the global route of the circuit design to identify potential global hot spots and modifying the global route based on any identified potential global hot spots to produce a detailed route;
providing, by using the computer, a second photolithography hot spot filter having a second set of hot spot conditions, the second set of hot spot conditions being less pessimistic than the first set of hot spot conditions and configured to identify potential hot spots in the detailed route;
applying, by using the computer, the second hot spot filter to the detailed route to identify potential detailed hot spots and modifying the detailed route to produce a post-detailed route based on any identified potential detailed hot spots; and
performing a rip-up and reroute of the post-detailed route to produce a layout, wherein the performing a rip-up and reroute of the post-detailed route comprises:
providing a third photolithography hot spot filter having a third set of hot spot conditions, the third set of hot spot conditions being less pessimistic than the second set of hot spot conditions and configured to identify potential post-detail hot spots in the post-detailed route;
predicting the location of post-detail hot spots within the post-detailed route by applying the third set of hot spot conditions to the post-detail route;
defining a hot spot window around each of the predicted post-detail hot spots in the post-detail route; and
performing a rip-up and reroute of the wires within the each of the defined hot spot windows only such that the produced layout is hot spot free.
2. The method of claim 1 , wherein the rip-up and reroute of the wires within each of the hot spot windows limits the rerouting of any vias.
3. The method of claim 2 , wherein the rip-up and reroute of the wires within each of the hot spot windows limits the rerouting of any vias to positions that do not affect any other layers.
4. The method of claim 3 , wherein the rip-up and reroute of the wires within each of the hot spot windows completely prohibits the rerouting of any vias.
5. The method of claim 1 , wherein the first, second, and third photolithography hot spot filters each comprise a plurality of hot spot rules.
6. The method of claim 1 , wherein the circuit design and the layout are in a computer-aided design format.
7. The method of claim 6 , wherein the rip-up and reroute of the post-detailed route is performed at least partially by a computer-aided system.
8. The method of claim 7 , wherein the rip-up and reroute of the post-detailed route is performed entirely by a computer-aided system.