Deposition of ZrA1ON films
Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.
1. A method of forming a gate dielectric, comprising:
exposing a substrate surface at a temperature between 250° C. to 350° C. to a precursor material including zirconium tertiary-butoxide and trimethyl-aluminum simultaneously for a time period of between 0.3 to 2.0 seconds;
exposing the substrate surface to at least one first purge material selected from hydrogen, helium, neon, nitrogen, and argon for a time period of between 1 to 5 seconds;
exposing the substrate surface to at least one reactant material including water vapor, oxygen, hydrogen peroxide, ozone and nitrous oxide for a time period of between 0.5 to 5.0 seconds to form a first dielectric material having a thickness ranging from 0.1 to 0.2 nanometers and a formula of approximately ZrAlON;
exposing the substrate surface to at least one second purge material selected from hydrogen, helium, neon, nitrogen, and argon for a time period of between 1 to 5 seconds to complete a first deposition cycle to form a first dielectric layer having a first thickness; and
repeating the first deposition cycle to form additional dielectric layers having the first thickness until a final dielectric material thickness is obtained.
2. The method of claim 1 , wherein the ZrAlON layer comprises a substantially continuous layer having a root mean square surface roughness of less than 0.5 nanometers and a current leakage rate of less than 1.1×10 −7 amps per cm 2 at an electric field strength of 1 megavolt per cm.
3. The method of claim 1 , further including:
forming metallization lines in a metal layer disposed above and in contact with the ZrAlON layer to form a gate electrode in an integrated circuit; and
annealing the device in a H 2 ambient after forming the metallization lines.
4. The method of claim 1 , wherein the first dielectric material has a formula of Zr X Al 2−X O Y N 2−Y , where X and Y are each from 0.5 to 1.5.
5. A method comprising:
forming a dielectric layer on a substrate comprising a zirconium aluminum oxynitride layer, including:
exposing a substrate surface to a precursor material including a zirconium-containing compound and an aluminum-containing compound simultaneously in a first deposition cycle;
exposing the substrate surface to at least one first purge material in the first deposition cycle;
exposing the substrate surface to at least one reactant material to form a first dielectric material having a first thickness and a formula of Zr A Al B O X N Y (A>0, B>0, X>0, Y>0) in the first deposition cycle;
exposing the substrate surface to at least one second purge material to complete the first deposition cycle; and
repeating the first deposition cycle to form additional dielectric layers, each having the first thickness, until a final dielectric material thickness is obtained.
6. The method of claim 5 , wherein the method includes forming an electrically conductive layer on the dielectric layer.
7. The method of claim 6 , wherein forming an electrically conductive layer on the dielectric layer includes forming one or more of a metal, doped polysilicon, a silicided metal, a polycide, tantalum nitride, or a conductive organic compound.
8. The method of claim 5 , wherein exposing the substrate surface to at least one first purge material includes exposing the substrate surface to material selected from hydrogen, helium, neon, nitrogen, and argon.
9. The method of claim 5 , wherein exposing the substrate surface to at least one reactant material includes exposing the substrate surface to reactant material selected from water vapor, oxygen, hydrogen peroxide, ozone and nitrous oxide.
10. The method of claim 5 , wherein exposing the substrate surface to at least one second purge material includes exposing the substrate surface to material selected from hydrogen, helium, neon, nitrogen, and argon.
11. The method of claim 5 , wherein exposing a substrate surface to a precursor material including a zirconium-containing compound and an aluminum-containing compound includes exposing a substrate surface to a precursor material including a mixture of zirconium tertiary-butoxide and tri-methyl-aluminum.
12. The method of claim 5 , wherein exposing the substrate surface to at least one reactant material to form Zr A Al B O X N Y (A>0, B>0, X>0, Y>0) includes forming Zr X Al 2−X O Y N 2−Y , where X and Y each range from 0.5 to 1.5.
13. The method of claim 5 , wherein forming a dielectric layer on a substrate includes forming the dielectric layer on silicon-based substrate.
14. The method of claim 5 , wherein forming a dielectric layer includes forming the dielectric having a nanolaminate structure.
15. The method of claim 14 , wherein forming the dielectric having a nanolaminate structure includes forming the nanolaminate structure in a NROM (non-volatile read-only memory) flash memory device.
16. The method of claim 5 , wherein the method includes forming the dielectric layer in an integrated circuit configured to couple to a controller.
17. The method of claim 5 , wherein exposing a substrate surface to a precursor material includes exposing a substrate surface to Zr[(CH 3 ) 2 ] 4 , Zr[(C 2 H 5 ) 2 ] 4 , or Zr[(CH 3 )(C 2 H 5 )] 4 .
18. The method of claim 5 , wherein exposing a substrate surface to a precursor material includes exposing a substrate surface to Al(CH 3 ) 3 , AlH 3 , or N(CH 3 ) 2 (C 2 H 5 ).
19. The method of claim 5 , wherein exposing the substrate surface to at least one reactant material includes exposing the substrate surface to NH 3 .
20. The method of claim 5 , wherein the method includes forming the dielectric layer in a memory.
21. The method of claim 5 , wherein controlling the forming of the dielectric layer to form the dielectric layer having a root mean square surface roughness that is less than one tenth of the layer thickness.
22. The method of claim 5 , wherein the method includes forming the dielectric layer separated from the substrate by a diffusion barrier.