Junction field effect transistor input buffer level shifting circuit

1. A method of interfacing between a first semiconductor device including junction field effect transistors (JFETs) and a bus, comprising the steps of:

receiving an input signal having a first voltage swing at an input terminal of the first semiconductor device including JFETs;

translating the input signal to an internal signal having a second voltage swing lower than the first voltage swing;

providing the input signal onto the bus from a second semiconductor device operating at a second power supply voltage higher than a first power supply voltage at which the first semiconductor device operates;

receiving the internal signal by core circuitry including JFETs and operating at a first power supply voltage;

providing a second internal signal having essentially the second voltage swing from the core circuitry; and

translating the second internal signal to an output signal having essentially the first voltage swing.

2. The method of claim 1 , wherein:

the first voltage swing is substantially greater than the second voltage swing.

3. The method of claim 1 , wherein:

the first power supply voltage is essentially the same value as the second voltage swing.

4. The method of claim 1 , wherein:

the second voltage swing is about 0.5 volts.

5. The method of claim 1 , further including:

providing the input signal onto the bus from a second semiconductor device operating at a second power supply voltage higher than a first power supply voltage at which the first semiconductor device operates.

6. A system, comprising:

at least a first semiconductor device, comprising

an input buffer including at least one junction field effect transistor (JFET), the input buffer receiving an input signal having a first voltage swing and providing a shifted signal having a second voltage swing lower than the first voltage swing; and

core circuitry comprising JFETs, the core circuitry coupled to receive the shifted signal wherein the core circuitry operates from a first power supply having a magnitude less than the first voltage swing; and

an output buffer including at least one JFET, the output buffer coupled to receive a first signal having essentially the second voltage swing from the core circuitry and providing an output signal having essentially the first voltage swing.

7. The semiconductor device of claim 6 , wherein:

the first semiconductor device further includes a higher voltage section coupled to and formed in the same substrate as the output buffer, the higher voltage section operating at a power supply level greater than the first power supply.

8. The semiconductor device of claim 7 , wherein:

the higher voltage section comprises insulated gate field effect transistors (IGFETs).

9. The system of claim 6 , further including:

at least a second semiconductor device coupled to the output buffer of the first semiconductor device by at least one signal line, the second semiconductor device operating at a power supply level greater than the first power supply.

10. The system of claim 6 , further including:

the first power supply has a magnitude of less than a forward bias voltage of a pn junction formed by at least one of the JFETs in the core circuitry and the core circuitry includes complementary JFETs.

11. The system of claim 6 , further including:

at least a second semiconductor device coupled to the input buffer of the first semiconductor device by at least one signal line, the second semiconductor device operating at a power supply level greater than the first power supply.

12. The semiconductor device of claim 6 , wherein:

the first semiconductor device further includes a higher voltage section formed in the same substrate as the input buffer circuit and coupled thereto, the higher voltage section operating at a power supply level greater than the first power supply.

13. The semiconductor device of claim 11 , wherein:

the higher voltage section comprises insulated gate field effect transistors (IGFETs).