Reconfigurable integrated circuits with scalable architecture including a plurality of special function elements
An integrated circuit (IC) includes a number of function blocks (FB), of which at least one is re-configurable. Each of the FBs may be a reconfigurable function or a non-reconfigurable function or recursively expanded with additional “nested” function blocks. The IC further includes a number of input pins, a number of output pins, an adder, and a number of crossbar devices. The elements, at least at the IC level, are coupled in a manner such that all input signals are provided to the FBs through a first subset of the crossbar devices, all internal signals are routed from one FB to another FB through a second subset of crossbar devices, and all output signals are routed from the FBs to the output pins through a third subset of crossbar devices. To increase routability and speed each of the crossbar device output has a single fanout. Additionally, each of the crossbar devices may provide only one input to each other crossbar device. In some embodiments, an FB may include special function elements, and optionally, (cascaded) selection paths. Other embodiments may also be described.
1. An apparatus comprising:
a plurality of reconfigurable logic elements having first inputs and first outputs;
a plurality of special function elements having second inputs and second outputs, wherein a subset of the first outputs are coupled to the second inputs, and wherein the special function elements include multiple ones selected from the group consisting of a subtractor, an arithmetic logic unit, a multiplier, a floating point unit, a memory array, and an adder that includes one or more fast carry logic blocks; and
a plurality of crossbar devices having third inputs and third outputs, wherein the plurality of crossbar devices are configured to selectably couple a subset of the third inputs to first or second outputs, and wherein a subset of the third outputs are coupled to the first and second inputs.
2. The apparatus of claim 1 , further comprising a plurality of multiplexors coupled to the first and second outputs, and wherein the plurality of multiplexors are configured to selectively couple the first or the second outputs to the subset of the third inputs.
3. The apparatus of claim 2 , further comprising a plurality of registers correspondingly coupled to the multiplexors, and wherein the registers are configured to store output signals of selected ones of the first or second outputs.
4. The apparatus of claim 3 , further comprising a second plurality of multiplexors coupled to the multiplexors, and wherein the plurality of registers are configured to selectively couple:
the selected ones of the first or second outputs, without intermediate storage, or
the stored output values of the selected first or second outputs to the subset of the third inputs.
5. The apparatus of claim 1 , wherein the special function elements include a plurality of adders, with each of the plurality of adders having one or more fast carry logic blocks.
6. The apparatus of claim 5 , wherein the plurality of adders includes a first adder having first one or more fast carry logic blocks, and a second adder having second one or more fast carry logic blocks, and wherein the first and second carry logic blocks are configured to connect a carry-out of the first adder to a carry-in of the second adder.
7. The apparatus of claim 1 , further comprising a plurality of inputs and a plurality of outputs, wherein the plurality of inputs are coupled to a second subset of the third inputs, and wherein the plurality of outputs are coupled to a second subset of the third outputs.
8. The apparatus of claim 1 , further comprising a function block comprising the configurable logic elements, the special function elements, and the crossbar devices.
9. The apparatus of claim 8 , further comprising another function block similarly constituted as said function block.
10. The apparatus of claim 9 , wherein the other function block is nested in said function block.
11. The apparatus of claim 9 , further comprising additional crossbar devices coupling the function blocks to each other.
12. The apparatus of claim 11 , further comprising a plurality of inputs and a plurality of outputs, wherein the plurality of inputs are coupled to a subset of inputs of the additional crossbar devices, and the plurality of outputs are coupled to a subset of outputs of the additional crossbar devices.
13. The apparatus of claim 1 , wherein said apparatus is an embedded logic block of an integrated circuit.
14. The apparatus of claim 1 , wherein said apparatus is an integrated circuit.
15. A method comprising:
reconfigurably routing a plurality of data signals to a plurality of reconfigurable logic elements as well as to a plurality of special function elements, wherein the special function elements include multiple ones selected from the group consisting of a subtractor, an arithmetic logic unit, a multiplier, a floating point unit, a memory array, and an adder having one or more fast carry logic blocks;
selecting outputs from the reconfigurable logic elements or special function elements; and
reconfigurably routing the selected outputs to the plurality of reconfigurable logic elements as well as to the plurality of special function elements.
16. The method of claim 15 , wherein said selecting comprises selecting by a plurality of multiplexors.
17. The method of claim 16 , further comprising storing output signals of the selected outputs.
18. The method of claim 17 , further comprising selecting either the outputs selected by the multiplexors, or the stored output signals of the selected outputs.
19. The method of claim 15 , wherein a subset of said reconfigurably routed data signals comprises one or more input data signals.
20. The method of claim 15 , wherein said reconfigurably routing the selected outputs comprises reconfigurably routing a subset of the selected outputs as output signals.
21. The method of claim 15 , wherein said reconfigurably routing a plurality of data signals, said selecting outputs, and said reconfigurably routing the selected outputs are performed in a function block of an apparatus.
22. The method of claim 21 , wherein said reconfigurably routing a plurality of data signals, said selecting outputs, and said reconfigurably routing of the selected outputs are collectively performed within each of a plurality of function blocks of an apparatus.