IP Library › Granted Patent US 7,772,866
Granted Patent B2
US 7,772,866 · App. 11/683,058 · Granted Aug 10, 2010

Structure and method of mapping signal intensity to surface voltage for integrated circuit inspection

Assignees: International Business Machines Corporation; Samsung Electronics Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,772,866
App. No.
11/683,058
Granted
Aug 10, 2010
Kind
B2
Abstract

Embodiments of the present invention provide a test structure for inspection of integrated circuits. The test structure may be fabricated on a semiconductor wafer together with one or more integrated circuits. The test structure may include a common reference point for voltage reference; a plurality of voltage dropping devices being connected to the common reference point; and a plurality of electron-collecting pads being connected, respectively, to a plurality of contact points of the plurality of voltage dropping devices. A brightness shown by the plurality of electron-collecting pads during an inspection of the integrated circuits may be associated with a pre-determined voltage.

Claims (29)

1. A test structure fabricated together with one or more integrated circuits on a semiconductor wafer, said test structure comprising:

a common reference point for voltage reference;

a plurality of voltage dropping devices connected to said common reference point; and

a plurality of electron-collecting pads connected to a plurality of contact points, respectively, of said plurality of voltage dropping devices, a brightness shown by said plurality of electron-collecting pads during an inspection of said integrated circuits representing a pre-determined voltage at locations of said plurality of electron-collecting pads.

2. A test structure according to claim 1 , wherein said common reference point is a ground point having a zero voltage during said inspection of said integrated circuits.

3. A test structure according to claim 2 , wherein said plurality of voltage dropping devices are a group of diodes with said contact points being the anode thereof, said group of diodes being connected in a series with the cathode of a diode being connected to the anode of a preceding diode except a first diode in said series.

4. A test structure according to claim 3 , wherein the cathode of said first diode is connected to said common reference point.

5. A test structure according to claim 1 , wherein said plurality of voltage dropping devices are a group of transistors with a gate of said transistors being connected to either a source or a drain of said transistors, said transistors having a pre-determined voltage drop from the source to the drain of said transistors during operation.

6. A test structure according to claim 5 , wherein said group of transistors being connected in a series with the drain of a transistor being connected to the source of an adjacent transistor.

7. A test structure according to claim 1 , wherein said plurality of voltage dropping devices are a group of n-type field-effect-transistors (NFETs); sources of said NFETs being connected to said common reference point; drains of said NFETs being connected to said plurality of electron-collecting pads; and gates of said NFETs being connected to a common testing pad.

8. A test structure according to claim 1 , wherein said plurality of voltage dropping devices are a group of p-type field-effect-transistors (PFETs); drains of said PFETs being connected to said common reference point; sources of said PFETs being connected to said plurality of electron-collecting pads; and gates of said PFETs being connected to a common testing pad.

9. A test structure fabricated upon a semiconductor wafer having one or more integrated circuits, said test structure comprising:

a common reference point for voltage reference;

a plurality of voltage dropping devices having respectively a first and a second contact points, said first contact point being associated with said common reference point, said voltage dropping devices being adapted to hold up to a certain pre-determined value of voltages between said first and said second contact points respectively; and

a plurality of conductive pads being connected respectively to said second points of said voltage dropping devices, said conductive pads being adapted to hold electronic charges and showing certain brightness representing said pre-determined voltages at locations of said plurality of electron-collecting pads during an inspection of said one or more integrated circuits.

10. A test structure according to claim 9 , wherein said common reference point is a ground point having a pre-known voltage during said inspection of said one or more integrated circuits.

11. A test structure according to claim 10 , wherein said plurality of voltage dropping devices are a group of semiconductor diodes connected in a series with said first contact point being the anode and said second contact point being the cathode thereof, and wherein the cathode of a diode being connected to the anode of a neighboring diode except the first diode in said series being connected to said common reference point.

12. A test structure according to claim 9 , wherein said plurality of voltage dropping devices are a group of transistors with a gate being connected to a source or a drain depending on the type of said transistors, said transistors having a pre-determined voltage drop from the source to the drain during operation.

13. A test structure according to claim 12 , wherein said group of transistors are connected in a series with the drain of a transistor being connected to the source of an adjacent transistor.

14. A structure, comprising:

a substrate having a ground point;

a plurality of semiconductor devices having respectively first and second contact points, said first contact points being associated with said ground point, said semiconductor devices being adapted to hold, up to a pre-determined set of values of, voltages between said first and said second contact points; and

a plurality of conductive pads being connected to said second contact points of said semiconductor devices respectively, said conductive pads being adapted to collect electronic charges and showing certain brightness representing said pre-determined voltages at locations of said plurality of electron-collecting pads during an inspection of one or more integrated circuits.

15. The structure of claim 14 , wherein one or more of said plurality of semiconductor devices are semiconductor diodes having an anode and a cathode respectively, said semiconductor diodes having a pre-determined threshold voltage from said anode to said cathode during operation.

16. The structure of claim 14 , wherein one or more of said plurality of semiconductor devices are semiconductor transistors having a gate, a source, and a drain, said gate being connected to said source, wherein said semiconductor transistors being adapted to provide certain voltage drops between said source and said drain when being turned on.

17. A test structure according to claim 14 , wherein said plurality of voltage dropping devices are a group of diodes and said first and second contact points being the anode and cathode thereof respectively, said group of diodes being connected in a series with the cathode of a diode being connected to the anode of a neighboring diode.

18. A test structure according to claim 17 , wherein the cathode of a first diode in said series is connected to said common reference point.

19. A test structure according to claim 14 , wherein said plurality of voltage dropping devices are a group of transistors and a gate of said transistors being connected to a source or a drain of said transistors, said transistors having a pre-determined voltage drop from the source to the drain of said transistors during operation.

20. A test structure according to claim 19 , wherein said group of transistors being connected in a series with the drain of a transistor being connected to the source of an adjacent transistor.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2007
From: SUN, MIN-CHUL
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 019002/0527 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2007
From: PATTERSON, OLIVER D.; WILDMAN, HORATIO SEYMOUR
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 019002/0538 →
Continuity (1)
Related Publication 20080217612A1 · Sep 11, 2008