One-transistor static random access memory with integrated vertical PNPN device
View Patent ↗A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is electrically common to the emitter/collector of the FET and a base of the NPN of the PNPN device is electrically common to the channel region of the FET. The anode pin of the PNPN device may be used as a word line or a bit line. A method of forming the 1T SRAM device is also disclosed.
1. A structure comprising:
a planar n-channel field effect transistor (NFET) on a surface of the structure; and
a vertical PNPN device integrated to the planar NFET by one side of the planar NFET, a top P type region of the vertical PNPN device being located on the surface of the structure;
wherein a drain of the NFET is coupled to a bit line and a gate of the NFET is coupled to a word line, and wherein a source of the NFET comprises a collector of an NPN of the PNPN device and a base of a PNP of the PNPN device.
2. The structure of claim 1 , wherein the vertical PNPN device includes a P+ type diffusion region on the surface of the structure, an N type diffusion region, a P type channel of the NFET (PWELL) and a N+ type triple well (TWELL).
3. The structure of claim 2 , wherein the PNPN device extends from the surface of the structure to a P type substrate of the structure and includes in order: the P+ type diffusion region, the N type diffusion region, the PWELL and the TWELL.
4. The structure of claim 2 , further comprising an insulation trench adjacent to a side of the structure.
5. The structure of claim 4 , wherein the insulation trench separates the P+ type diffusion region, the N type diffusion region and the PWELL from a nearby structure.
6. The structure of claim 5 , wherein the insulation trench extends to a depth intermediate between a bottom of the PWELL and a bottom of the TWELL.
7. The structure of claim 2 , wherein the P+ type diffusion region is separated from the PWELL by the N type diffusion region.
8. The structure of claim 2 , wherein a ground bus is integrated to the TWELL.
9. A one-transistor static random access memory (SRAM) structure comprising:
a planar n-channel field effect transistor (NFET) on a surface of the structure; and
a vertical PNPN device integrated to the planar NFET by one side of the planar NFET, a top P type region of the vertical PNPN device being located on the surface of the structure;
wherein a drain of the NFET is coupled to a bit line and a gate of the NFET is coupled to a word line, and wherein a source of the NFET comprises a collector of an NPN of the PNPN device and a base of a PNP of the PNPN device.
10. The SRAM structure of claim 9 , wherein an N type source of the NFET is electrically common to an N type base of a PNP device of the PNPN device, the N type base also being electrically common to an N type collector of an NPN device of the PNPN device.
11. The SRAM structure of claim 9 , wherein a P type channel region of the NFET is electrically common to a P type base of an NPN device of the PNPN device, the P type base also being electrically common to a collector of a PNP device of the PNPN device.
12. The SRAM structure of claim 11 , further comprising an insulation trench adjacent to a side of the structure, the insulation trench separating the P type channel region and the P type base from a nearby structure.
13. The SRAM structure of claim 12 , wherein the insulation trench extends to a depth intermediate between a bottom of the P type channel region and a bottom of an N+ type triple well underneath the P type channel region, the N+ type triple well being electrically common to an emitter of the NPN device.
14. An integrated circuit comprising:
a one-transistor static random access memory (1T SRAM) device, the SRAM device including:
a planar n-channel field effect transistor (NFET) on a surface of the structure; and
a vertical PNPN device integrated to the planar NFET by one side of the planar NFET, a top P type region of the vertical PNPN device being on the surface of the structure;
wherein a drain of the NFET is coupled to a bit line and a gate of the NFET is coupled to a word line, and wherein a source of the NFET comprises a collector of an NPN of the PNPN device and a base of a PNP of the PNPN device.
15. The integrated circuit of claim 14 , further including multiple 1T SRAM devices arranged in a row, the word line being coupled to a gate of an NFET of each of the multiple 1T SRAM devices, wherein an anode of a vertical PNPN device of each of the multiple 1T SRAM devices is coupled to another word line.
16. The integrated circuit of claim 14 , further including multiple 1T SRAM devices arranged in a column, the bit line being coupled to a drain of an NFET of each of the multiple 1T SRAM devices, wherein an anode line of a vertical PNPN device of each of the multiple 1T SRAM devices is coupled to another bit line.
17. The integrated circuit of claim 14 , wherein a source of the NFET, a collector of an NPN of the PNPN device, and a base of a PNP of the PNPN device are coupled together.
18. The integrated circuit of claim 14 , wherein a collector of a PNP of the PNPN device and a base of an NPN of the PNPN device are coupled together.