Dual port gain cell with side and top gated read transistor
View Patent ↗A DRAM memory cell and process sequence for fabricating a dense (20 or 18 square) layout is fabricated with silicon-on-insulator (SOI) CMOS technology. Specifically, the present invention provides a dense, high-performance SRAM cell replacement that is compatible with existing SOI CMOS technologies. Various gain cell layouts are known in the art. The present invention improves on the state of the art by providing a dense layout that is fabricated with SOI CMOS. In general terms, the memory cell includes a first transistor provided with a gate, a source, and a drain respectively; a second transistor having a first gate, a second gate, a source, and a drain respectively; and a capacitor having a first terminal, wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity.
1. A method of forming a semiconductor structure comprising:
providing a semiconductor-on-insulator substrate that comprises at least one via contact extending through an SOI layer and a buried insulating layer of said semiconductor-on-insulator substrate and at least one storage capacitor including a node conductor;
providing an oxide cap atop a portion of said node conductor, while leaving another portion of said node conductor exposed;
recessing the exposed portion of the node conductor and forming a conductive strap in said recess;
removing the oxide cap and forming a top trench oxide atop a portion of said node conductor and said conductive strap; and
forming a read wordline atop the top trench oxide and forming a write wordline atop an exposed surface of said SOI layer, wherein said read wordline is an element of a transistor which includes side-gating and a top gate.
2. The method of claim 1 further comprising forming a dopant region in said SOI layer surrounding said via contact.
3. The method of claim 1 further comprising forming a nitride layer after removing the oxide cap and prior to forming said top trench oxide.
4. The method of claim 1 wherein a dielectric material located within said storage trench is formed and serves as the gate dielectric of the side-gate.
5. The method of claim 1 further comprising at least one write wordline adjacent to said read wordline on a surface of said SOI layer including a transfer gate oxide located thereon.
6. The method of claim 1 further comprising forming borderless bitline contacts adjacent to at least said read wordline that extends down into said SOI layer.
7. The method of claim 6 further comprising a bitline conductor atop said borderless bitline contacts that run perpendicular to said read wordline.