Methods for isolating portions of a loop of pitch-multiplied material and related structures
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains. The select gates are biased in the off state to prevent current flow from the mid-portion of the loop's legs to the blocks, thereby electrically isolating the mid-portions from the ends of the loops and also electrically isolating different legs of a loop from each other.
1. A method, comprising:
providing a substrate having a plurality of loops formed of semiconductor material, each of the loops defined by first and second elongated portions joined at a first end and at a second opposing end of the each of the loops, wherein the first ends of the loops are interjoined by conductive material and the second ends of the loops are interjoined by conductive material; and
forming each of a first pair of transistors along each first elongated portion of each of the loops, wherein one transistor of each of the first pair of transistors is proximate the first end of the loops and another transistor of each of the first pair of transistors is proximate the second end of the loops, wherein each loop forms an active area of each one of the first pair of transistors.
2. The method of claim 1 , wherein each of the first pair of transistors is disposed along each of the first elongated portions, further comprising forming each of a second pair of transistors along each of the second elongated portion of each of said loops, each loop forming an active area of each one of the second pair of transistors.
3. The method of claim 1 , wherein providing the substrate having the loop comprises forming the loop using pitch multiplication.
4. The method of claim 3 , wherein forming the loop using pitch multiplication comprises:
forming a mandrel over the substrate;
forming a spacer on sidewalls of the mandrel;
removing the mandrels to leave a pattern of free-standing spacers; and
etching a pattern defined by the free-standing spacers into a layer comprising the semiconductor material.
5. The method of claim 1 , wherein providing the substrate having the loop comprises providing a plurality of lines of semiconductor material, wherein the lines are each contiguous with a block of semiconductor material at the loop end.
6. The method of claim 1 , wherein forming the first pairs of transistors comprises doping either side of the active area to form source/drain regions.
7. The method of claim 6 , wherein forming the first pairs of transistors comprises forming transistors gate directly over the loop, the transistor gates defining the active regions thereunder.
8. The method of claim 7 , wherein one of each of the loop ends is a source region and wherein forming the first pairs of transistors comprises shunting together the source region and the transistor gates.