Methods to reduce the critical dimension of semiconductor devices
A method of forming features on a target layer. The features have a critical dimension that is triple- or quadruple-reduced compared to the critical dimension of portions of a resist layer used as a mask. An intermediate layer is deposited over a target layer and the resist layer is formed over the intermediate layer. After patterning the resist layer, first spacers are formed on sidewalls of remaining portions of the resist layer, masking portions of the intermediate layer. Second spacers are formed on sidewalls of the portions of the intermediate layer. After removing the portions of the intermediate layer, the second spacers are used as a mask to form the features on the target layer. A partially fabricated integrated circuit device is also disclosed.
1. A method of forming features on a target layer, comprising:
forming openings in a resist layer located above an intermediate layer, the intermediate layer located above a target layer to be patterned;
forming substantially vertical first spacers on sidewalls of the resist layer;
removing remaining portions of the resist layer and portions of the intermediate layer not masked by the substantially vertical first spacers to expose portions of the target layer;
removing the substantially vertical first spacers to expose a top surface of remaining portions of the intermediate layer;
forming substantially vertical second spacers on the sidewalls of the remaining portions of the intermediate layer;
removing the remaining portions of the intermediate layer; and
forming features in exposed portions of the target layer.
2. The method of claim 1 , wherein forming features in exposed portions of the target layer comprises forming the features having a critical dimension that is smaller than the critical dimension of the openings in the resist layer.
3. The method of claim 1 , wherein forming openings in a resist layer comprises forming the openings having a critical dimension of x and producing remaining portions of the resist layer having a critical dimension of x.
4. The method of claim 3 , wherein forming features in exposed portions of the target layer comprises forming features having a critical dimension equal to about x/3.
5. The method of claim 1 , wherein forming openings in a resist layer comprises forming the openings having a critical dimension of 5x/4 and producing remaining portions of the resist layer having a critical dimension of 3x/4.
6. The method of claim 5 , wherein forming features in exposed portions of the target layer comprises forming features having a critical dimension equal to about x/4.
7. The method of claim 1 , wherein forming substantially vertical first spacers on sidewalls of the resist layer comprises depositing a spacer material at a thickness about equal to a critical dimension of features to be formed on the target layer.
8. The method of claim 1 , wherein at least one of forming substantially vertical first spacers on sidewalls of the resist layer and forming substantially vertical second spacers on the sidewalls of the remaining portions of the intermediate layer comprises forming the substantially vertical first spacers or the substantially vertical second spacers from silicon oxide or silicon nitride.
9. The method of claim 1 , wherein forming substantially vertical first spacers on sidewalls of the resist layer comprises conformally depositing a spacer material over remaining portions of the resist layer.
10. The method of claim 1 , wherein removing remaining portions of the resist layer and portions of the intermediate layer not masked by the substantially vertical first spacers to expose portions of the target layer comprises etching remaining portions of the resist layer between the substantially vertical first spacers and etching portions of the intermediate layer not masked by the substantially vertical first spacers.
11. The method of claim 1 , further comprising selecting a material for the intermediate layer to be selectively etchable relative to the materials of the substantially vertical first spacers and the substantially vertical second spacers.
12. The method of claim 10 , further comprising forming an anti-reflective layer between the resist layer and the intermediate layer.