Method and apparatus providing integrated circuit having redistribution layer with recessed connectors
A method of making a semiconductor die includes forming a trench around a conductive stud extending from the first side to a second side of a substrate to expose a portion of the stud and then forming a conductive layer inside the trench and in electrical contact with the stud.
1. A semiconductor die, comprising:
a substrate having a first side and a second side;
an integrated circuit formed on the second side of the substrate;
a stud arranged through the substrate and electrically coupling the integrated circuit to the first side of the substrate;
a trench arranged in the substrate around the stud and extending away from the stud;
a first dielectric layer arranged in the trench; and
a conductive layer arranged in the trench on the first dielectric layer and electrically coupled to the stud, wherein the conductive layer comprises a first bond pad, a second bond pad, and a conductive trace connecting the first bond pad and the second bond pad.
2. The semiconductor die of claim 1 , further comprising a second dielectric layer arranged over the conductive layer and the first dielectric layer.
3. The semiconductor die of claim 2 , wherein a portion of the conductive layer arranged away from the stud is not covered by the second dielectric layer.
4. The semiconductor die of claim 1 , further comprising a dielectric layer arranged around the through wafer interconnect stud.
5. The semiconductor die of claim 1 , further comprising a redistribution line electrically coupling the integrated circuit to the stud.
6. The semiconductor die of claim 1 , wherein the stud is substantially perpendicular to the plane of the substrate.
7. The semiconductor die of claim 1 , wherein the stud is surrounded by at least one dielectric layer.
8. The semiconductor die of claim 1 , wherein the conductive layer comprises at least one of aluminum, copper, an alloy of aluminum, and an alloy of copper.
9. The semiconductor die of claim 2 , wherein the stud is not covered by the second dielectric layer.
10. A semiconductor die comprising:
a substrate;
integrated circuitry arranged in an active surface of the substrate;
a stud arranged through the substrate and electrically coupled to the integrated circuitry;
a first bond pad electrically coupled to the integrated circuitry via the stud;
a second bond pad; and
a conductive trace,
wherein the first bond pad, the second bond pad and the conductive trace are arranged in a trench on a back surface of the substrate, the back surface being arranged opposite the active surface.
11. The semiconductor die of claim 10 , wherein the conductive stud is arranged substantially perpendicular to a plane of the substrate.
12. The semiconductor die of claim 10 further comprising redistribution lines electrically connecting the integrated circuitry to the conductive stud.
13. An electronic device comprising:
a semiconductor die comprising:
a substrate;
integrated circuitry arranged in a first surface of the substrate;
a trench arranged in a second surface of the substrate;
a first dielectric layer arranged entirely within the trench;
a conductive redistribution layer arranged entirely within the trench and on the first dielectric layer, the conductive redistribution layer being electrically coupled to the electronic device; and
a conductive stud extending into the conductive redistribution layer and electrically coupling the integrated circuitry to the conductive redistribution layer.
14. The semiconductor die of claim 13 , wherein the conductive redistribution layer comprises a first bond pad.
15. The semiconductor die of claim 14 , wherein the first bond pad is in electrical contact with the conductive stud.
16. The semiconductor die of claim 14 , wherein the conductive redistribution layer further comprises a second bond pad and a conductive trace electrically coupling the second bond pad to the first bond pad.
17. The semiconductor die of claim 13 , wherein the conductive redistribution layer comprises at least one of aluminum, copper, an alloy of aluminum, and an alloy of copper.
18. The semiconductor die of claim 16 further comprising a second dielectric layer arranged over at least the first bond pad and the conductive trace.
19. The semiconductor die of claim 16 , wherein the second bond pad is connected to the electronic device.