Process for improving the reliability of interconnect structures and resulting structure
View Patent ↗An interconnect structure of an integrated circuit having improved reliability and a method for forming the same are provided. The method includes providing a substrate, forming a dielectric layer overlying the substrate, performing a first shrinking process, wherein the dielectric layer shrinks and has a first shrinkage rate, forming a conductive feature in the dielectric layer after the step of performing the first shrinking process, and performing a second shrinking process after the step of forming the conductive feature, wherein the dielectric layer substantially shrinks and has a second shrinkage rate.
1. A method for forming an interconnect structure of an integrated circuit, the method comprising:
providing a substrate;
forming a dielectric layer having a k value of less than 3.5 overlying the substrate;
forming an opening in the dielectric layer;
filling the opening with a metallic material to form a metallic feature;
performing a treatment to the dielectric layer to cause a shrinkage in the dielectric layer after the step of filling the opening, wherein a top surface of the dielectric layer between the metallic feature and a neighboring metallic feature has a curve with an edge portion higher than a central portion; and
after the step of performing the treatment, forming a cap dielectric layer over and contacting the dielectric layer.
2. The method of claim 1 further comprising performing an additional treatment to the dielectric layer before the step of filling the opening.
3. The method of claim 2 , wherein the treatment and the additional treatment comprise a UV curing at a wavelength of less than 365 nm.
4. The method of claim 1 , wherein a ratio of a height of the curve to a horizontal length of the curve is greater than 0.14 when a spacing between the metallic feature and the neighboring metallic feature is less than 0.3 μm and the horizontal length is less than 1500 Å.
5. The method of claim 4 , wherein the ratio is greater than 0.2.
6. The method of claim 1 further comprising a selective removal of top portions of the dielectric layer after the step of forming the metallic feature.
7. The method of claim 1 , wherein the step of performing the treatment and the step of performing the additional treatment are both performed when the top surface of the dielectric layer is exposed.
8. The method of claim 2 , wherein the step of performing the treatment and the step of performing the additional treatment are both performed when no additional layer is over and contacting the top surface of the dielectric layer.