Technique for forming an isolation trench as a stress source for strain engineering
By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the device to an oxidizing ambient at elevated temperatures, thereby incorporating silicon dioxide into the non-oxidizable material. Hence, an increased compressive stress may be generated within the non-oxidizable layer.
1. A method, comprising:
forming a non-oxidizable layer within an isolation trench formed in a Semiconductor layer located above a substrate;
selectively modifying said non-oxidizable layer within said isolation trench by treating at least a portion of said non-oxidizable layer by an ion bombardment and exposing said portion to an oxidizing ambient after said ion bombardment and prior to depositing any insulating material in said isolation trench to generate compressive stress;
filling said isolation trench with said insulating material after selectively modifying said non-oxidizable layer to generate said compressive stress; and
forming a transistor element adjacent to said isolation trench, said compressive stress inducing a lattice strain in said transistor element.
2. The method of claim 1 , wherein said non-oxidizable layer comprises silicon and nitride.
3. The method of claim 2 , wherein selectively modifying said non-oxidizable layer comprises forming a mask layer to expose said non-oxidizable layer within said isolation trench and treating said exposed portion of said non-oxidizable layer by said ion bombardment.
4. The method of claim 3 , wherein said oxidizing ambient is an oxidizing plasma ambient.
5. The method of claim 1 , wherein said ion bombardment is generated by an ion implantation process.
6. A method, comprising:
depositing a non-oxidizable layer having an intrinsic stress above a first isolation trench and a second isolation trench, said first and second isolation trenches being formed in a semiconductor layer;
selectively modifying said intrinsic stress of said non-oxidizable layer in said first isolation trench by treating said non-oxidizable layer in said first isolation trench by an ion bombardment and exposing said non-oxidizable layer to an oxidizing ambient after said ion bombardment and prior to depositing any insulating material in said first isolation trench to generate compressive stress in said non-oxidizable layer; and
filling said first and second isolation trenches with said insulating material after selectively modifying said non-oxidizable layer to generate said compressive stress.
7. The method of claim 6 , wherein said oxidizing ambient is an oxidizing plasma ambient.
8. The method of claim 6 , wherein said ion bombardment is generated by an ion implantation process.
9. The method of claim 6 , wherein said non-oxidizable layer comprises silicon and nitride.
10. The method of claim 6 , wherein said non-oxidizable layer is deposited with an intrinsic tensile stress.
11. The method of claim 6 , further comprising forming a first transistor in a first semiconductor region bordered by said first isolation trench and forming a second transistor in a second semiconductor region bordered by said second isolation trench.
12. The method of claim 11 , wherein said first transistor is a P-channel transistor and said second transistor is an N-channel transistor.