IP Library Granted Patent US 7,847,400
Granted Patent B2
US 7,847,400 · App. 12/114,517 · Granted Dec 7, 2010

Semiconductor package substrate structure and manufacturing method thereof

Assignee: Unimicron Technology Corp.
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Quick Facts
Patent No.
US 7,847,400
App. No.
12/114,517
Granted
Dec 7, 2010
Kind
B2
Abstract

A semiconductor package substrate structure and a manufacturing method thereof are disclosed. The structure includes a substrate having a plurality of electrical connecting pads formed on at least one surface thereof; a plurality of electroplated conductive posts each covering a corresponding one of the electrical connecting pads and an insulating protective layer formed on the surface of the substrate and having a revealing portion for exposing the electroplated conductive posts therefrom. The invention allows the interval between the electroplated conductive posts to be minimized, the generation of concentrated stresses and the overflow of underfill to be avoided, as well as the reduction of the overall height of the fabricated package.

Claims (10)

1. A semiconductor package substrate structure, comprising:

a substrate with a plurality of electrically connecting pads formed on at least one surface thereof;

a plurality of electroplated conductive posts each fully covering a corresponding one of the electrically connecting pads; and

an insulating protective layer formed on the substrate with a revealing portion for exposing the electroplated conductive posts,

wherein the revealing portion is a plurality of openings penetrating the insulating protective layer for exposing a portion of the substrate while fully exposing the tops and sides of the electroplated conductive posts.

2. A semiconductor package substrate structure, comprising:

a substrate with a plurality of electrically connecting pads formed on at least one surface thereof;

a plurality of electroplated conductive posts each fully covering a corresponding one of the electrically connecting pads; and

an insulating protective layer formed on the substrate with a revealing portion for exposing the electroplated conductive posts,

wherein the revealing portion is a groove penetrating the insulating protective layer for exposing a portion of the substrate while fully exposing the tops and sides of the electroplated conductive posts.

Assignments (2)
MERGER Recorded Oct 19, 2010
From: PHOENIX PRECISION TECHNOLOGY CORPORATION
To: UNIMICRON TECHNOLOGY CORP.
Reel/Frame 025158/0923 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 2, 2008
From: HU, WEN-HUNG
To: PHOENIX PRECISION TECHNOLOGY CORPORATION
Reel/Frame 020895/0043 →
Priority Claims (1)
TW 96115687 A · May 3, 2007 · national
Continuity (1)
Related Publication 20080272501A1 · Nov 6, 2008