BEOL interconnect structures with improved resistance to stress
A chip is provided which includes a back-end-of-line (“BEOL”) interconnect structure. The BEOL interconnect structure includes a plurality of interlevel dielectric (“ILD”) layers which include a dielectric material curable by ultraviolet (“UV”) radiation. A plurality of metal interconnect wiring layers are embedded in the plurality of ILD layers. Dielectric barrier layers cover the plurality of metal interconnect wiring layers, the dielectric barrier layers being adapted to reduce diffusion of materials between the metal interconnect wiring layers and the ILD layers. One of more of the dielectric barrier layers is adapted to retain compressive stress while withstanding UV radiation sufficient to cure the dielectric material of the ILD layers, making the BEOL structure better capable of avoiding deformation due to thermal and/or mechanical stress.
1. A chip including a back-end-of-line (“BEOL”) interconnect structure, comprising:
a plurality of interlevel dielectric (“ILD”) layers, said plurality of ILD layers including a dielectric material curable by ultraviolet (“UV”) radiation;
a plurality of metal interconnect wiring layers, each embedded in one of said plurality of ILD layers; and
a plurality of dielectric barrier layers, each covering one of said plurality of metal interconnect wiring layers, said plurality of dielectric barrier layers adapted to reduce diffusion of materials between said plurality of metal interconnect wiring layers and said plurality of ILD layers, at least some of said plurality of dielectric barrier layers being adapted to retain compressive stress while withstanding UV radiation sufficient to cure said dielectric material of said ILD layers.
2. The chip as claimed in claim 1 , wherein said plurality of ILD layers and said plurality of dielectric barrier layers together have an effective dielectric constant of less than 3.0.
3. The chip as claimed in claim 1 , wherein each of said dielectric barrier layers includes a plurality of sublayers.
4. The chip as claimed in claim 1 , wherein at least one of said plurality of dielectric barrier layers includes a post-deposition treated layer including a low-K silicon-containing material.
5. The chip as claimed in claim 4 , wherein said at least one dielectric barrier layer includes SiCNH, said at least one dielectric barrier layer having a top surface and a hydrogen concentration gradient in a direction normal to said top surface.
6. The chip as claimed in claim 1 , wherein said plurality of metal interconnect wiring layers include first wiring layers having a first thickness and second wiring layers having a second thickness greater than said first thickness, wherein said plurality of dielectric barrier layers includes at least one layer including silicon nitride having a compressive stress, said at least one layer being disposed between adjacent ones of said first wiring layer and said second wiring layer, and, otherwise, said plurality of dielectric barrier layers including a second dielectric material, said second dielectric material having a dielectric constant lower than a dielectric constant of silicon nitride.
7. The chip as claimed in claim 6 , wherein said second dielectric material includes SiCNH.
8. The chip as claimed in claim 1 , wherein at least one of said plurality of dielectric barrier layers includes a first layer including a low-K dielectric material adjacent to one of said metal interconnect wiring layers and a second layer including at least one of silicon nitride or silicon dioxide overlying said first layer.
9. The chip as claimed in claim 8 , wherein said first layer includes at least one of SiCNH, SiCOH, or SiCH.
10. The chip as claimed in claim 1 , wherein at least one of said plurality of ILD layers includes SiCOH and at least one of said plurality of dielectric barrier layers includes porous SiCOH.
11. The chip as claimed in claim 1 , wherein said BEOL interconnect structure is free of stress cracks.
12. The chip as claimed in claim 1 , wherein at least ones of said dielectric barrier layers are compressive stressed.
13. The chip as claimed in claim 1 , wherein at least ones of said dielectric barrier layers are compressive stressed between about −0.1 GPa and about −0.5 GPa.