Phase change memory structure with multiple resistance states and methods of programming and sensing same
A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states.
1. A resistive memory cell, comprising:
a plurality of phase change resistance elements provided between a single first electrode and a single second electrode, each of said resistance elements having a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of others of said resistance elements.
2. The resistive memory cell of claim 1 , wherein the plurality of phase change resistance elements comprises two phase change resistance elements.
3. The resistive memory cell of claim 2 , wherein at a first programming voltage the first and second resistance elements are in a low resistance state, at a second programming voltage the first element is in a high resistance state while the second element is in a low resistance state, at a third programming voltage the first element is in a low resistance state while the second element is in a high resistance state, and at a forth programming voltage the first and second elements are in a high resistance state.
4. The resistive memory cell of claim 2 , wherein the first resistance element has a first length and the second resistance element has a second length less than the first length.
5. The resistive memory cell of claim 2 , wherein the second resistance element is doped such that the second resistance element has a resistance different than a resistance of the first resistance element.
6. The resistive memory cell of claim 1 , wherein the plurality of phase change elements comprises three phase change elements.
7. The resistive memory cell of claim 6 , wherein at a first programming voltage first, second, and third elements are in a low resistance state, at a second programming voltage the first element is in a high resistance state while the second and third elements are in a low resistance state, at a third programming voltage the first and second elements are in a high resistance state while the third element is in a low resistance state, at a forth programming voltage the first and second elements are in a low resistance state while the third element is in a high resistance state, at a fifth programming voltage, the first element is in a low resistance state while the second and third elements are in a high resistance state, and at a sixth programming voltage the first, second, and third elements are in a high resistance state.
8. The resistive memory cell of claim 1 , wherein the plurality of phase change resistance elements comprises four or more phase change resistance elements.
9. The resistive memory cell of claim 1 , wherein the memory cell is capable of storing at least two bits.
10. The resistive memory cell of claim 2 , wherein the first resistance element has a first width and the second resistance element has a second width greater than the first width.
11. The resistive memory cell of claim 1 , wherein the resistive memory cell is a stacked cell.
12. The resistive memory cell of claim 11 , wherein said single first and second electrodes function as respective first and second conductive sidewalls formed on either side of said resistance elements.
13. The resistive memory cell of claim 1 , wherein the resistive memory cell is a vertical cell.
14. The resistive memory cell of claim 4 , wherein said first electrode has an elongated portion used to shorten the distance between said first electrode and said second electrode in a portion of the resistive memory cell containing the second resistance element.
15. The resistive memory cell of claim 4 , wherein said second electrode has an elongated portion used to shorten the distance between said first electrode and said second electrode in a portion of the resistive memory cell containing the second resistance element.
16. The resistive memory cell of claim 1 , wherein the resistive memory cell is a planar cell.
17. A memory device, comprising:
an array of memory cells, each memory cell comprising:
a plurality of phase change resistance elements provided between a single first electrode and a single second electrode, each of said resistance elements having a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of others of said resistance elements.
18. The memory device of claim 17 , wherein the plurality of phase change elements comprises two phase change elements.
19. The memory device of claim 18 , wherein at a first programming voltage the first and second phase change elements are in a low resistance state, at a second programming voltage the first phase change element is in a high resistance state while the second phase change element is in a low resistance state, at a third programming voltage the first phase change element is in a low resistance state while the second phase change element is in a high resistance state, and at a forth programming voltage the first and second phase change elements are in a high resistance state.
20. The memory device of claim 17 , wherein the plurality of phase change elements comprises three or more phase change elements.
21. The memory device of claim 17 , wherein each of the memory cells is a vertical cell.
22. The memory device of claim 17 , wherein each of the memory cells is a planar cell.
23. The memory device of claim 17 , wherein each memory cell is capable of storing at least two bits.
24. The memory device of claim 17 , further comprising a readout circuitry comprising a plurality of multi-state sense amplifiers.
25. The memory device of claim 24 , wherein each multi-state sense amplifier determines a resistance state of a respective memory cell by comparing a readout voltage corresponding to a resistance of the respective memory cell with a readout voltage corresponding to a reference resistance.