Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors
View Patent ↗Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
1. A method of forming a p-type field effect transistor, said method comprising:
providing a substrate having a top surface;
forming a silicon germanium layer on said top surface of said substrate;
forming a gate stack on said silicon germanium layer, said gate stack comprising a high-k gate dielectric layer in contact with said silicon germanium layer above a designated channel region;
one of before said forming of said gate stack and after said forming of said gate stack, performing an implant process using a dopant material having negatively charged ions; and
performing additional processing to complete said field effect transistor, said performing of said additional processing comprising performing at least one thermal process so as to cause said dopant material to diffuse into said gate dielectric layer leaving a predetermined concentration of said dopant material at an interface between said gate dielectric layer and said silicon germanium layer in order to selectively adjust a threshold voltage of said field effect transistor to between −0.3V and −0.45V,
said performing of said implant process comprising, before said forming of said gate dielectric layer:
forming a protective layer on said substrate;
implanting said dopant material through said protective layer into said silicon germanium layer without damaging said silicon germanium layer; and
removing said protective layer,
said at least one thermal process causing said dopant material to diffuse directly from said silicon germanium layer into said gate dielectric layer.
2. The method according to claim 1 , said forming of said protective layer comprising performing a high temperature oxide deposition process.
3. The method according to claim 1 , further comprising, after said forming of said gate stack and before said performing of said implant process, forming at least one layer of sidewall spacers adjacent to opposing sidewalls of said gate stack.
4. The method according to claim 1 , said performing of said additional processing comprising performing additional processing to complete a p-type field effect transistor and said negatively charged ions at said interface effectively reducing a negative threshold voltage of said p-type field effect transistor.
5. The method according to claim 4 , said dopant material comprising any of chlorine, bromine and iodine.
6. The method according to claim 1 , said dopant material comprising fluorine and said predetermined concentration being between 1×10 12 atoms/cm 2 and 1×10 13 atoms/cm 2 .
7. The method according to claim 1 , said gate stack further comprising a metal gate conductor layer on said high-k gate dielectric layer.
8. A method of forming a complementary metal oxide semiconductor device, said method comprising:
providing a substrate having a top surface;
forming a silicon germanium layer on said top surface over a first region of said substrate, but not over a second region of said substrate;
forming a first gate stack for a p-type field effect transistor on said silicon germanium layer over said first region and a second gate stack for an n-type field effect transistor on said substrate over said second region, said first gate stack comprising a high-k gate dielectric layer in contact with said silicon germanium layer above a designated channel region for said p-type field effect transistor;
one of before said forming of said first gate stack and said second gate stack and after said forming of said first gate stack and said second gate stack, masking said second region and performing an implant process using a dopant material having negatively charged ions; and
performing additional processing to complete said p-type field effect transistor and said n-type field effect transistor, said performing of said additional processing comprising performing at least one thermal process to cause said dopant material to diffuse into said high-k gate dielectric layer of said first gate stack leaving a predetermined concentration of said dopant material at an interface between said high-k gate dielectric layer and said silicon germanium layer in order to selectively reduce a negative threshold voltage of said p-type field effect transistor to between −0.3V and −0.45V.
9. The method according to claim 8 , said performing of said implant process comprising, before said forming of said first gate stack and said second gate stack, forming a protective layer on said silicon germanium layer, performing said implant process such that said dopant material is implanted through said protective layer and into said silicon germanium layer without damaging said silicon germanium layer, and removing said protective layer; and,
said at least one thermal process causing said dopant material to diffuse directly from said silicon germanium layer into said high-k gate dielectric layer.
10. The method according to claim 9 , said forming of said protective layer comprising performing a high temperature oxide deposition process.
11. The method according to claim 8 , further comprising, after said forming of said first gate stack and said second gate stack and before said performing of said implant process, forming at least one layer of gate sidewall spacers adjacent to opposing sidewalls of said first gate stack and said second gate stack.
12. The method according to claim 8 , said dopant material comprising any of chlorine, bromine and iodine.
13. The method according to claim 8 , said dopant material comprising fluorine and said predetermined concentration being between 1×10 12 atoms/cm 2 and 1×10 13 atoms/cm 2 .
14. The method according to claim 8 , said forming of said first gate stack and said second gate stack being performed such that said first gate stack comprises a near valence band metal gate conductor layer adjacent to said high-k gate dielectric layer said second gate stack comprises a second high-k gate dielectric layer on said substrate over said second region and a near conduction band metal gate conductor layer adjacent to said second high-k gate dielectric layer.