Semiconductor device with bonding pad
View Patent ↗A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern.
1. A method for forming a semiconductor device with a bonding pad, the method comprising:
providing a first substrate having an upper surface and a bottom surface, the upper surface comprising a device area and a bonding area;
forming semiconductor device elements in the device area;
forming a bonding pad over the upper surface of the first substrate in the bonding area;
forming an interconnect structure comprising a plurality of inter-metal dielectric layers, via plugs and metal patterns within the inter-metal dielectric layers over the bonding pad, wherein a surface of the interconnect structure closest to the bonding pad is the bottom surface of the interconnect structure;
bonding a top surface of the interconnect structure to a second substrate;
forming an opening from the bottom surface side through the first substrate to expose the bond pad, and attaching a wire bond passing through the opening to the exposed bond pad;
wherein the interconnect structure is disposed between the bonding pad and the second substrate.
2. The method of claim 1 , further comprising a step of thinning the first substrate before the step of forming an opening through the first substrate.
3. The method of claim 1 , wherein the second substrate comprises a material selected from the group of glass, plastic material, and ceramic material.
4. The method of claim 1 , wherein the step of forming an opening through the first substrate comprises wet etching the first substrate with an etchant containing a KOH or HF solution.
5. The method of claim 1 , wherein the via plugs and metal patterns encased within the inter-metal dielectric layers electrically connect the semiconductor elements to the bond pad.
6. The method of claim 1 , further comprising a step of depositing an etch stop layer over the bonding area and the device area, wherein the etch stop layer is interposed between the upper surface of the first substrate and the interconnect structure.
7. The of claim 1 , further comprising a step of forming a shallow trench isolation structure in the bonding region.
8. The of claim 1 , wherein the semiconductor elements comprise CMOS image sensors.