Method for selectively forming strain in a transistor by a stress memorization technique without adding additional lithography steps
A selective stress memorization technique is disclosed in which the creation of tensile strain may be accomplished without additional photolithography steps by using an implantation mask or any other mask required during a standard manufacturing flow, or by providing a patterned cap layer for a strained re-crystallization of respective drain and source areas. In still other aspects, additional anneal steps may be used for selectively creating a crystalline state and a non-crystalline state prior to the re-crystallization on the basis of a cap layer. Thus, enhanced strain may be obtained in one type of transistor while not substantially negatively affecting the other type of transistor without requiring additional photolithography steps.
1. A method, comprising:
forming an etch stop layer above a P-channel transistor and an N-channel transistor;
forming a cap layer above said etch stop layer;
forming a mask above said cap layer, said mask exposing a first portion of said cap layer located above said P-channel transistor and covering a second portion of said cap layer located above said N-channel transistor;
removing at least a part of said first portion by using said etch stop layer and by using said mask as an etch mask;
implanting a P-type dopant species into said P-channel transistor using said mask as an implantation mask;
removing said mask;
forming a further implantation mask covering said P-channel transistor and exposing said second portion of said cap layer;
introducing an N-type dopant species through said second portion of said cap layer formed above said etch stop layer and into said N-channel transistor on the basis of said further implantation mask; and
annealing said P-channel transistor and said N-channel transistor in the presence of said second portion of said cap layer formed above said etch stop layer after introducing said N-type dopant species through said second portion of said cap layer and into said N-channel transistor on the basis of said further implantation mask.
2. The method of claim 1 , further comprising forming drain and source regions in a non-crystalline state in said N-channel transistor prior to forming said cap layer.
3. The method of claim 2 , further comprising removing said second portion of said cap layer and forming metal silicide regions in said P-channel transistor and said N-channel transistor.
4. The method of claim 1 , wherein removing at least a part of said first portion of said cap layer comprises maintaining a portion of said first portion of said cap layer to form a first sidewall spacer on sidewalls of a gate electrode structure of said P-channel transistor.
5. The method of claim 4 , further comprising forming a protective layer on said first sidewall spacer prior to removing said mask covering the second portion of said cap layer.
6. The method of claim 1 , further comprising forming a second sidewall spacer on sidewalls of a gate electrode of said N-channel transistor from said second portion of said cap layer after introducing said N-type dopant species.