Multi-state memory cell with asymmetric charge trapping
A multi-state NAND memory cell is comprised of two drain/source areas in a substrate. An oxide-nitride-oxide structure is formed above the substrate between the drain/source areas. The nitride layer acting as an asymmetric charge trapping layer. A control gate is located above the oxide-nitride-oxide structure. An asymmetrical bias on the drain/source areas causes the drain/source area with the higher voltage to inject an asymmetric distribution hole by gate induced drain leakage injection into the trapping layer substantially adjacent that drain/source area.
1. A method for erasing a multi-state NAND memory cell having a control gate, first and second active areas, and a trapping layer adapted for asymmetrical trapping of first and second data bits near each of the active areas, the method comprising:
applying a positive voltage to the control gate; and
grounding the first and second active areas to erase the first and second data bits by gate induced drain leakage hole injection into the trapping layer.
2. The method of claim 1 wherein a threshold voltage is reduced by injected holes that neutralize electrons from a previous erased condition.
3. The method of claim 1 wherein the memory cell is configured to tunnel electrons into the trapping layer from a uniform sheet of charge in an inversion region in a substrate.
4. The method of claim 3 wherein the electrons tunneled into the trapping layer form a continuous, substantially uniform sheet of trapped charge in the trapping layer.
5. The method of claim 1 wherein the trapping layer is configured to be an oxide-nitride-oxide structure.
6. The method of claim 1 wherein the positive voltage on the control gate is in a range of 10-20V.
7. The method of claim 1 wherein the memory cell is configured to be part of a string of memory cells.
8. The method of claim 7 wherein the string of memory cells is configured to be part of an array of memory cells.
9. The method of claim 8 wherein each string of memory cells is configured to include select gate drain and select gate source transistors on opposite ends of the string of memory cells.
10. A method for erasing a multi-state NAND memory cell having a control gate, first and second source/drain regions, and a trapping layer capable of asymmetrical trapping of first and second data bits near each of the source/drain regions, the method comprising:
applying a positive voltage V H to the control gate; and
applying asymmetrical voltages to the first and second source/drain regions to erase the first and second data bits, wherein one of a gate-to-drain or a gate-to-source voltage is V H /2 in response to which of the first or second data bits are being erased.
11. The method of claim 10 wherein the memory cell is part of a selected column of memory cells.
12. The method of claim 10 wherein the memory cell is part of a row of memory cells biased by V WL voltages coupled to the control gate.
13. A method for erasing a multi-state NAND memory cell having a control gate, first and second source/drain regions, and a trapping layer capable of asymmetrical trapping of first and second data bits near each of the source/drain regions, the method comprising:
applying a voltage to the control gate; and
performing gate induced drain leakage hole injection from the first and second source/drain regions substantially simultaneously to erase both the first and second data bits.