Controlled boosting in non-volatile memory soft programming
A soft programming pre-charge voltage provides boosting control during soft programming operations for non-volatile memory devices. A pre-charge voltage can be applied to the word lines of a block of memory cells to enable pre-charging of the channel region of a NAND string to be inhibited from soft programming. The level of boosting in the channel region of the inhibited NAND string is governed by the pre-charge voltage and the soft programming voltage. By controlling the pre-charge voltage, more reliable and consistent channel boosting can be achieved. In one embodiment, the pre-charge voltage is increased between applications of the soft programming voltage to reduce or eliminate a rise in the channel's boosted potential. In one embodiment, the soft programming pre-charge voltage level(s) is determined during testing that is performed as part of a manufacturing process.
1. A method of soft programming non-volatile memory, comprising:
applying a first voltage to a set of word lines to enable pre-charging of a first set of non-volatile storage elements coupled to said set of word lines, said first voltage is different from a read pass voltage;
while said first voltage is applied to each word line in said set of word lines, applying an inhibit voltage to a bit line for said first set of non-volatile storage elements to pre-charge a channel region of said first set of non-volatile storage elements; and
while said inhibit voltage is applied to said bit line for said first set of non-volatile storage elements, applying a second voltage to said set of word lines to soft program a second set of non-volatile storage elements coupled to said set of word lines, said second voltage is higher than said first voltage.
2. The method of claim 1 , further comprising:
verifying that said second set of non-volatile storage elements is not soft programmed after applying said second voltage;
applying a third voltage to said set of word lines to enable pre-charging of said first set of non-volatile storage elements, said third voltage is higher than said first voltage;
while said third voltage is applied to each word line in said set of word lines, applying said inhibit voltage to said bit line for said first set of non-volatile storage elements to pre-charge said channel region of said first set of non-volatile storage elements; and
while said inhibit voltage is applied to said bit line for said first set of non-volatile storage elements, applying a fourth voltage to said set of word lines to soft program said second set of non-volatile storage elements, said fourth voltage is higher than said second voltage.
3. The method of claim 2 , wherein:
a difference between a level of said fourth voltage and a level of said third voltage is equal to a difference between a level of said second voltage and a level of said first voltage.
4. The method of claim 1 , wherein:
applying said inhibit voltage to said first set of non-volatile storage elements begins after applying said first voltage to said set of word lines begins and before applying said second voltage to said set of word lines begins.
5. The method of claim 1 , wherein:
said first set of non-volatile storage elements is a NAND string of non-volatile storage elements.
6. The method of claim 1 , further comprising:
verifying that said second set of non-volatile storage elements is not soft programmed after applying said second voltage;
applying a third voltage to said set of word lines to enable pre-charging of said first set of non-volatile storage elements;
while said third voltage is applied to each word line in said set of word lines, applying said inhibit voltage to said bit line for said first set of non-volatile storage elements to pre-charge said channel region of said first set of non-volatile storage elements; and
while said inhibit voltage is applied to said bit line for said first set of non-volatile storage elements, applying a fourth voltage to said set of word lines to soft program said second set of non-volatile storage elements, said fourth voltage is higher than said second voltage;
wherein a difference between a level of said fourth voltage and said third voltage is different than a difference between a level of said second voltage and said first voltage.
7. A method of soft programming non-volatile memory, comprising:
applying a first pre-charge enable voltage to a set of word lines coupled to a first set of non-volatile storage elements and a second set of non-volatile storage elements;
pre-charging a channel region of said first set of non-volatile storage elements while applying said first pre-charge enable voltage to said set of word lines;
applying a first soft programming voltage to said set of word lines after pre-charging said channel region of said first set of non-volatile storage elements;
applying a second pre-charge enable voltage to said set of word lines after applying said first soft programming voltage, said second pre-charge enable voltage is higher than said first pre-charge enable voltage;
pre-charging a channel region of said first set of non-volatile storage elements while applying said second pre-charge enable voltage to said set of word lines; and
applying a second soft programming voltage to said set of word lines after pre-charging said channel region of said first set of non-volatile storage elements, said second soft programming voltage is higher than said first soft programming voltage.
8. The method of claim 7 , further comprising:
applying an inhibit voltage to a bit line associated with said first set of non-volatile storage elements after beginning application of said first pre-charge enable voltage to said set of word lines and before beginning application of said first soft programming voltage.
9. The method of claim 8 , further comprising:
applying an enable voltage to a bit line associated with said second set of non-volatile storage elements prior to applying said first soft programming voltage.
10. The method of claim 7 , wherein:
a difference between a level of said first soft programming voltage and a level of said first pre-charge enable voltage is equal to a difference between a level of said second soft programming voltage and a level of said second pre-charge enable voltage.
11. The method of claim 7 , wherein:
a difference between a level of said first soft programming voltage and said first pre-charge enable voltage is different than a difference between a level of said second soft programming voltage and a level of said second pre-charge enable voltage.
12. The method of claim 7 , wherein:
said first pre-charge enable voltage is different from a read pass voltage applied to unselected ones of said word lines when reading said first set of non-volatile storage elements and said second set of non-volatile storage elements.
13. The method of claim 7 , wherein:
said second pre-charge enable voltage is different from a read pass voltage applied to unselected ones of said word lines when reading said first set of non-volatile storage elements and said second set of non-volatile storage elements.
14. The method of claim 7 , wherein:
said first set of non-volatile storage elements is a first NAND string; and
said second set of non-volatile storage elements is a second NAND string.
15. A method of soft-programming non-volatile memory, comprising:
simultaneously applying a first programming voltage pulse to each word line of a set of word lines, said first programming voltage pulse including a first pre-charge enable voltage followed by a first soft programming voltage; and
after applying said first programming voltage pulse, simultaneously applying a second programming voltage pulse to each word line of said set of word lines, said second programming voltage pulse including a second pre-charge enable voltage followed by a second soft programming voltage, said second pre-charge enable voltage is higher than said first pre-charge enable voltage and said second soft programming voltage is higher than said first soft programming voltage.
16. The method of claim 15 , wherein:
a difference between said first soft programming voltage and said first pre-charge enable voltage is equal to a difference between said second soft programming voltage and said second pre-charge enable voltage.
17. The method of claim 15 , wherein:
a difference between said first soft programming voltage and said first pre-charge enable voltage is different than a difference between said second soft programming voltage and said second pre-charge enable voltage.
18. The method of claim 15 , further comprising, while applying said first programming voltage pulse and said second programming voltage pulse;
applying an inhibit voltage to a bit line for a first NAND string and applying an enable voltage to a bit line for a second NAND string, said first NAND string and said second NAND string are coupled to said set of word lines.
19. The method of claim 15 , wherein:
said first pre-charge enable voltage and said second pre-charge enable voltage are different from a read pass voltage applied to unselected ones of said word lines when reading said non-volatile memory.