Method of fabricating integrated circuitry
The invention includes methods of fabricating integrated circuitry. In one implementation, at least two different elevation conductive metal lines are formed relative to a substrate. Then, interconnecting vias are formed in a common masking step between, a) respective of the at least two different elevation conductive metal lines, and b) respective conductive nodes. Interconnecting conductive metal is provided within the interconnecting vias. Other aspects and implementations are contemplated.
1. A method of fabricating integrated circuitry, comprising:
forming first and second conductive nodes on a semiconductor substrate;
forming a first conductive metal line over the first conductive node, the first conductive node and the first conductive metal line having a first interlevel dielectric therebetween, the first conductive metal line having a laterally enlarged portion with first dielectric material extending internally therethrough and over the first conductive node;
forming a second conductive metal line over the first conductive metal line, the first and second conductive metal lines having a second interlevel dielectric therebetween, the second conductive metal line having a laterally enlarged portion with second dielectric material extending internally therethrough and over the second conductive node;
forming a third interlevel dielectric material over the second conductive metal line;
in a common masking step, first etching a second contact opening into and through the third interlevel dielectric effective to expose the laterally enlarged portion of the second conductive metal line, into and through the second dielectric material effective to expose internal side portions of the second conductive metal line, into and through the second interlevel dielectric, and into and through the first interlevel dielectric effective to extend the second opening to the second conductive node; and second etching a first contact opening into and through the third and second interlevel dielectrics effective to expose the laterally enlarged portion of the first conductive metal line, into and through the first dielectric material effective to expose internal side portions of the first conductive metal lines, and into and through the first interlevel dielectric effective to extend the first opening to the first conductive node, the first and second etchings leaving some of the first dielectric material extending internally through the first conductive metal line and some of the second dielectric material extending internally through the second conductive metal line; and
providing interconnecting conductive material within the extended first and second openings effective to electrically connect the first conductive metal line with the first conductive node and the second conductive metal line with the second conductive node.
2. The method of claim 1 wherein the first and second etchings etch internal side portions of the first and second conductive metal lines.
3. The method of claim 1 wherein the first and second etchings occur during a plurality of etching steps common to etching of the first and second openings.
4. The method of claim 1 wherein the first and second conductive nodes constitute two different nodes.
5. The method of claim 1 wherein the first and second conductive nodes constitute a single, common node.
6. The method of claim 1 wherein the first, second and third interlevel dielectrics, and the first and second dielectric materials, are common in composition.
7. The method of claim 1 wherein conductive portions of each of the first and second conductive metal lines consist essentially of metal.
8. The method of claim 1 wherein all conductive portions of each of the first and second conductive metal lines consist essentially of metal.
9. The method of claim 1 wherein the first and second conductive nodes have outer surfaces received at a common elevation and to which the first and second openings are formed.
10. The method of claim 1 wherein the first and second conductive lines have respective outermost surfaces which are globally planar.