Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor
A thread switch mechanism and technique for a microprocessor is disclosed wherein a processing of a first thread is completed, and a continuation of a second thread is initiated during completion of the first thread. In one form, the technique includes processing a first thread at a pipeline of a processing device, and initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event. The technique can also include initiating a instruction progress metric in response the context switch event. The technique can further include enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric.
1. A method comprising:
processing a first thread at a pipeline of a processing device;
initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event;
initiating an instruction progress metric in response to the context switch event;
enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric; and
flushing instructions of the first thread from the back end of the pipeline in response to the expiry of the instruction progress metric.
2. The method of claim 1 , further comprising flushing instructions of the first thread that are at the front end of the pipeline in response to the occurrence of the context switch event.
3. The method of claim 2 , further comprising:
processing instructions of the second thread at the front end upon flushing instructions of the first thread at the front end; and
initiating processing instructions of the second thread at the back end in response to detecting completion of the processing of instructions of the first thread at the back end.
4. The method of claim 1 wherein the instruction progress metric is based on at least one criterion selected from the group consisting of: a number of fetches, a number of memory accesses, a number of instructions processed, and a number of uses of an execution resource.
5. The method of claim 1 , further comprising:
detecting processing of instructions of the second thread at the front end; and
initiating the instruction progress metric to a second instruction progress metric value upon detecting a second thread switch event.
6. The method of claim 5 , further comprising:
detecting processing of instructions of the second thread at the back end; and
decrementing the instruction progress metric in response to detecting a second thread switch event and further in response to processing the instructions of the second thread at the back end after detecting the second thread switch event.
7. The method of claim 6 , further comprising:
detecting completion of processing of instructions of the second thread at the front end;
detecting an expiry of the instruction progress metric; and
initiating a flushing of the instructions of the second thread at the back end in response to the expiry.
8. The method of claim 1 , further comprising:
detecting a non-expiry of the instruction progress metric;
maintaining processing of the instructions of the first thread at the back end; and
processing instructions of the second thread at the front end.
9. The method of claim 3 , further comprising:
detecting an increase in a number of instructions of the second thread at the back end;
detecting whether the instruction progress metric is at a maximum instruction progress metric value; and
incrementing the instruction progress metric in response to the instruction progress metric being less than the maximum instruction progress metric value.
10. A processing device comprising:
a pipeline comprising a front end and a back end;
front end control logic of the front end configured to flush instructions of a first thread from the front end and to initiate processing of instructions of a second thread at the front end in response to an occurrence of a context switch event;
an instruction progress metric configured to initiate a flush signal in response to the occurrence of the context switch event; and
back end control logic of the back end configured to enable completion of processing of instructions of the first thread that are at the back end at the occurrence of the context switch event and to flush instructions of the first thread from the back end in response to an expiry of the instruction progress metric.
11. The processing device of claim 10 , wherein the back end control logic is further configured to flush instructions of the first thread from the front end in response to the occurrence of the context switch event.
12. The processing device of claim 11 , wherein the pipeline is further configured to initiate executing the instructions of the second thread at the front end while maintaining execution of the instructions of the first thread at the back end.
13. The processing device of claim 11 , further comprising a maximum instruction progress metric value configured to be used with the instruction progress metric.
14. The processing device of claim 10 , wherein the instruction progress metric is configured to be decremented upon loading an instruction of the first thread into the back end.
15. The processing device of claim 14 , further comprising:
wherein the instruction progress metric is further configured to be initiated in response to a detection of the context switch event; and
wherein the instruction progress metric is further configured to be decremented using a clock signal associated with completion of a program of instructions of the second thread.
16. The processing device of claim 10 , wherein the instruction progress metric is further configured to be altered from a first value associated with a first number of instructions of a first program to a second value associated with a second number of instructions of a second program.
17. The processing device of claim 10 , wherein:
the front end control logic is further configured to enable processing of instructions of the second thread at the front end during processing of instructions at the first thread at the back end; and
the back end control logic is further configured to enable processing of instructions of the second thread at the back end upon completion of processing instructions of the first thread.
18. A method comprising:
processing a first thread at a pipeline of a processing device based on instructions from an instruction cache;
initiating processing of a second thread at a front end of the pipeline in response to an occurrence of a context switch event;
initiating an instruction progress metric in response to the context switch event, the instruction progress metric based on a counter value;
enabling completion of processing of instructions of the first thread that are at a back end of the pipeline at the occurrence of the context switch event until an expiry of the instruction progress metric; and
flushing instructions of the first thread from the back end of the pipeline in response to the expiry of the instruction progress metric.
19. The method of claim 18 , further comprising:
processing instructions of the second thread at the front end during flushing of the instructions of the first thread;
detecting completion of the processing of instructions of the first thread at the back end; and
initiating processing instructions of the second thread at the back end.
20. The method of claim 18 , further comprising:
detecting a non-expiry of the instruction progress metric;
maintaining processing of the instructions of the first thread at the back end; and
processing instructions of the second thread at the front end.