IP Library Granted Patent US 7,943,463
Granted Patent B2
US 7,943,463 · App. 12/417,038 · Granted May 17, 2011

Methods of semiconductor processing involving forming doped polysilicon on undoped polysilicon

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,943,463
App. No.
12/417,038
Granted
May 17, 2011
Kind
B2
Abstract

A number of methods are provided for semiconductor processing. One such method includes depositing a first precursor material on a surface at a particular temperature to form an undoped polysilicon. The method also includes depositing a second precursor material on a surface of the undoped polysilicon at substantially the same temperature, wherein the undoped polysilicon serves as a seed to accelerate forming a doped polysilicon.

Claims (28)

1. A method of semiconductor processing comprising:

forming undoped polysilicon on an oxide surface of a trench, the undoped polysilicon formed via depositing a disilane (Si 2 H 6 ) precursor material on the oxide surface at a process temperature below 450° C. and sufficient to induce thermal decomposition of the disilane precursor material into the undoped polysilicon; and

forming a boron-doped polysilicon on a surface of the undoped polysilicon within the trench at a substantially the same process temperature below 450° C. to prevent void formation within the trench, the doped polysilicon formed via depositing a silane (SiH 4 ) precursor material and a boron dopant material on the surface of the undoped polysilicon;

wherein a nucleation time associated with forming the boron-doped polysilicon on the surface of the undoped polysilicon within the trench at the process temperature below 450° C. is less than two minutes.

2. The method of claim 1 , wherein depositing the disilane precursor material on the oxide surface includes depositing the disilane precursor material on the surface of a trench having a width in a range of 20-30 nanometers and a depth of at least 50 nanometers.

3. The method of claim 1 , wherein the method includes forming the undoped polysilicon by chemical vapor deposition at the process temperature and a pressure that induces nucleation at around 2 minutes.

4. The method of claim 3 , wherein the method includes forming the boron-doped polysilicon by chemical vapor deposition over the formed undoped polysilicon at the process temperature and the pressure by inducing nucleation of the boron-doped polysilicon at around 1 minute.

5. The method of claim 4 , wherein the method includes forming the boron-doped and undoped polysilicon with the process temperature and the pressure at levels selected to induce conformal deposition in a substantially amorphous configuration in order to reduce void formation in the trench.

6. The method of claim 1 , wherein the method includes filling the trench with the undoped polysilicon and the boron-doped polysilicon to serve as a control gate in a non-volatile memory cell.

7. A method of semiconductor processing comprising:

depositing a disilane (Si 2 H) precursor material on a silicon dioxide (SiO 2 ) surface of a trench at a process temperature below 450° C. to form an undoped polysilicon seed material on the silicon dioxide surface of the trench via thermal decomposition of the disilane; and

depositing a silane (SiH 4 ) precursor material and a boron-containing dopant on a surface of the undoped polysilicon at substantially the same process temperature below 450° C. to form a void-free boron-doped polysilicon within the trench;

wherein a nucleation time associated with forming the void-free boron-doped polysilicon within the trench at the process temperature below 450° C. is less than two minutes.

8. The method of claim 7 , wherein depositing the disilane precursor material includes depositing disilane (Si 2 H 6 ) that undergoes thermal decomposition to the undoped polysilicon in a temperature range of 380-450° C.

9. The method of claim 7 , wherein depositing the silane precursor material includes depositing silane (SiH 4 ) and the boron-containing dopant that undergo thermal decomposition to the boron-doped polysilicon in a temperature range of 380-450° C.

10. The method of claim 9 , wherein forming the boron-doped polysilicon includes forming a P-type semiconductor structure in combination with the undoped polysilicon.

11. The method of claim 7 , wherein the method of semiconductor processing includes reducing a nucleation time of the silane precursor material at multiple sites on the undoped polysilicon.

12. The method of claim 11 , wherein reducing the nucleation time includes reducing a length of time for formation of a boron-doped polysilicon as compared to formation of the boron-doped polysilicon in the absence of the undoped polysilicon.

13. The method of claim 7 , wherein the method of semiconductor processing includes utilizing chemical vapor deposition to partially fill an unfilled portion of the trench on the surface of a semiconductor structure with the undoped polysilicon to a substantially uniform thickness on walls and a bottom of the unfilled portion of the trench and to fill a remainder of the trench with the boron-doped polysilicon.

14. A method of semiconductor processing comprising:

depositing a gaseous disilane (Si 2 H 6 ) in a trench on a solid silicon dioxide (SiO 2 ) surface of the trench at a temperature below 450° C. that induces thermal decomposition of disilane into an undoped polysilicon to cover walls and a bottom of the solid SiO 2 surface of the trench;

depositing a gaseous silane (SiH 4 ) and a gaseous boron-containing dopant on a surface of the undoped polysilicon at substantially the same temperature below 450° C.; and

inducing nucleation of the gaseous silane (SiH 4 ) and the gaseous boron-containing dopant and accelerating conformal forming of a boron-doped polysilicon by the undoped polysilicon serving as a seed in order to reduce void formation in the trench;

wherein a nucleation time associated with forming the boron-doped polysilicon within the trench at the temperature below 450° C. is less than two minutes.

15. The method of claim 14 , wherein the method includes forming the undoped polysilicon on the walls and the bottom of the solid SiO 2 surface of the trench to a substantially uniform thickness in a range of 1-7 nanometers.

16. The method of claim 14 , wherein depositing the silane and the boron-containing dopant includes inducing thermal decomposition thereof to form the boron-doped polysilicon in a temperature range of 380-450° C.

17. The method of claim 14 , wherein the method includes utilizing chemical vapor deposition with a substantially stable temperature in a range of 380-450° C. and with a substantially stable pressure in a range of 0.2-0.5 Torr to induce a substantially amorphous configuration of the boron-doped polysilicon.

18. The method of claim 14 , wherein the method includes adjusting flow rates of the gaseous silane and the gaseous boron-containing dopant during chemical vapor deposition such that the boron atom density in the boron-doped polysilicon is in a range of 0.1-1.0% per cubic centimeter of the boron-doped polysilicon.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2009
From: KHANDEKAR, ANISH; HILL, ERVIN T.; YU, JIXIN; HULL, JEFFERY B.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 022495/0055 →
Continuity (1)
Related Publication 20100255664A1 · Oct 7, 2010