Fabrication of self-aligned gallium arsenide MOSFETS using damascene gate methods
A method for fabricating a gallium arsenide MOSFET device is presented. A dummy gate is formed over a gallium arsenide substrate. Source-drain extensions are implanted into the substrate adjacent the dummy gate. Dummy spacers are formed along dummy gate sidewalls and over a portion of the source-drain extensions. Source-drain regions are implanted. Insulating spacers are formed on dummy oxide spacer sidewalls. A conductive layer is formed over the source-drain regions. The conductive layer is annealed to form contacts to the source-drain regions. The dummy gate and the dummy oxide spacers are removed to form a gate opening. A passivation layer is in-situ deposited in the gate opening. The surface of the passivation layer is oxidized to create an oxide layer. A dielectric layer is ex-situ deposited over the oxide layer. A gate metal is deposited over the dielectric layer to form a gate stack in the gate opening.
1. A method for fabricating a MOSFET device, the method comprising:
forming a dummy gate over a substrate;
implanting source-drain extensions into the substrate adjacent the dummy gate;
forming dummy spacers along the sidewalls of the dummy gate and over a portion of the source-drain extensions;
defining the source-drain regions adjacent the source drain extensions;
forming contacts to the source-drain regions;
removing the dummy gate and the dummy spacers to form a gate opening;
depositing in-situ a passivation layer in the gate opening;
forming an oxide layer on the passivation layer;
depositing ex-situ a dielectric layer over the oxide layer; and
depositing a gate metal over the dielectric layer to form a gate stack in the gate opening.
2. The method of claim 1 , wherein the substrate is comprised of gallium arsenide.
3. The method of claim 1 , wherein the substrate is comprised of undoped <100> oriented gallium arsenide.
4. The method of claim 1 , further comprising:
implanting and annealing source-drain regions adjacent the source-drain extensions after forming the dummy spacers; and
forming insulating spacers on the sides of the dummy spacers.
5. The method of claim 1 , wherein the source-drains regions are defined with a photoresist layer.
6. The method of claim 5 , further comprising:
forming a conductive layer over the photoresist layer; and
lifting off the photoresist layer and annealing the conductive layer to form the contacts to the source-drain regions.
7. The method of claim 1 , wherein the contacts are formed by evaporating a layer of gold germanium over the source-drain regions, evaporating a layer of nickel over the layer of gold geranium germanium and evaporating a layer of gold over the layer of nickel.
8. The method of claim 1 , further comprising:
depositing a layer of nitride after forming the contacts to the source-drain regions;
depositing a layer of oxide over the layer of nitride and planaraizing the oxide layer to the uppermost surface of the layer of nitride; and
etching the layer of oxide and layer of nitride to the uppermost surface of the dummy gate.
9. The method of claim 1 , wherein the oxide layer is formed on the passivation layer by oxidizing the surface of the passivation layer.
10. The method of claim 1 , wherein the dummy gates are comprised of oxide.
11. The method of claim 1 , wherein the passivation layer comprises amorphous silicon.
12. The method of claim 1 , wherein the oxide layer comprises silicon dioxide.
13. The method of claim 1 , wherein the dielectric layer comprises hafnium oxide.
14. The method of claim 1 , wherein the gate metal comprises polysilicon, tungsten, tantalum, titanium nickel, or combinations thereof.
15. A method for fabricating a gallium arsenide MOSFET device, the method comprising:
forming a dummy gate over a substrate of gallium arsenide;
implanting source-drain extensions adjacent the dummy gate;
forming dummy oxide spacers along the sidewalls of the dummy gate and over a portion of the source-drain extensions;
defining the source-drain regions adjacent the source-drain extensions;
forming alloy contacts to the source-drain regions;
removing the dummy gate and removing the dummy oxide spacers to form a gate opening;
depositing in-situ a layer of amorphous silicon;
forming a silicon dioxide layer on the amorphous silicon layer;
depositing ex-situ a layer of hafnium oxide over the silicon dioxide layer; and
depositing gate metal over the hafnium oxide layer to form a gate stack.
16. The method of claim 15 , wherein the alloy contacts comprise a layer of gold germanium over the source-drain regions, a layer of nickel over the layer of gold germanium and a layer of gold over the layer of nickel.
17. The method of claim 15 , wherein the dummy gate is comprised of polysilicon.
18. The method of claim 15 , wherein the amorphous silicon layer has a thickness of about 1.5 nm.
19. The method of claim 15 , wherein the silicon dioxide layer has a thickness of less than 1 nm.
20. The method of claim 15 , wherein the hafnium oxide layer has a thickness of about 10 nm.