Stress relief of a semiconductor device
A semiconductor device includes a die including an active region, a scribe region, and a perimeter, wherein the scribe region is closer to the perimeter than the active region. In one embodiment, the die further comprises a crack arrest structure formed in the scribe region, and wherein the crack arrest structure includes one of curva-linear shapes and polygonal shapes concentrically oriented around a common center located at or near at least one corner of the die.
1. A semiconductor device comprising:
a die comprising an active region and a die edge;
the die further comprising a scribe region outside a crack stop, wherein the crack stop at least partially surrounds the active region; and
the die further comprising a crack arrest structure, wherein at least a portion of the crack arrest structure is formed in the scribe region of the die, wherein the die further comprises:
a substrate,
a first layer overlying the substrate, wherein the first layer comprises metal,
a second layer overlying the first layer, wherein the second layer comprises metal,
a third layer overlying the second layer, wherein the third layer comprises metal, and
wherein the crack arrest structure comprises:
a first portion formed in the first layer, wherein the first portion has a first outer edge located at a first distance from the die edge;
a second portion formed in the second layer, wherein the second portion has a second outer edge located at a second distance from the die edge and the second distance is greater than the first distance; and
a third portion formed in the third layer, wherein the third portion has a third outer edge located at a third distance from the die edge, and wherein the third distance is greater than the second distance; and,
wherein the crack arrest structure extends from a first edge of the scribe region to a second edge of the scribe region and spaced from a corner formed by the first and second edges of the scribe region.
2. The semiconductor device of claim 1 further comprising an edge seal, wherein the edge seal at least partially surrounds the active region.
3. The semiconductor device of claim 1 , wherein the die further comprises corner regions and a non-corner region, wherein the non-corner region is devoid of the crack arrest structure and at least one of the corner regions comprises the crack arrest structure.
4. The semiconductor device of claim 3 , wherein the crack arrest structure comprises curva-linear shapes, wherein the curva-linear shapes are oriented from a common center at or near at least one corner of the die.
5. The semiconductor device of claim 3 , wherein the crack arrest structure comprises polygonal shapes, wherein the polygonal shapes are oriented from a common center at or near at least one corner of the die.
6. The semiconductor device of claim 1 , wherein the die is formed on a semiconductor wafer, the semiconductor wafer comprises a saw region adjacent the die edge and wherein the crack arrest structure does not extend into the saw region.
7. The semiconductor device of claim 1 , wherein the crack arrest structure further comprises a fourth portion formed in the first layer, wherein the fourth portion has a fourth outer edge located at a fourth distance from the die edge and the first distance is greater than the fourth distance.
8. The semiconductor device of claim 1 , wherein the crack arrest structure further comprises:
a fifth portion formed in the second layer, wherein the fifth portion has a fifth outer edge located at a fifth distance from the die edge, wherein the second distance is greater than the fifth distance; and
a sixth portion formed in the third layer, wherein the sixth portion has a sixth outer edge located at a sixth distance from the die edge, wherein the third distance is greater than the sixth distance.