Delay-lock loop and method adapting itself to operate over a wide frequency range
A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.
1. A system, comprising:
a frequency divider configured to receive an input signal and generate an output signal, the input signal having a frequency and the output signal generated by dividing the input signal by a value;
a delay line coupled to the frequency divider, the delay line configured to receive the output signal from the frequency divider and delay the output signal to generate a delayed output signal; and
an initialization circuit coupled to the programmable frequency divider and the delay line, the initialization circuit configured to receive the input signal and the delayed output signal, and to program the value based on the frequency of the input signal.
2. The system of claim 1 wherein the initialization circuit is configured to program the frequency divider to divide the input signal by a larger number as the frequency of the input signal increases.
3. The system of claim 1 wherein the delay line comprises a plurality of delay stages and further comprising a phase mixer, wherein phase signals from the delay stages are applied to the phase mixer, and wherein the phase mixer generates four signals, all of which having a frequency that is half of the frequency of the input signal, each of the four signals having a respective phase that is equally phase shifted from the other of the four signals and each of the four signals having transitions that coincide with transitions of the input signal.
4. The system of claim 1 wherein the initialization circuit being configured to program the value based on the frequency of the input signal comprises the initialization circuit being configured to program the value based on the frequency of the input signal relative to a minimum delay of the delay line.
5. The system of claim 1 further comprising a phase mixer coupled to the initialization circuit and the delay line, wherein the initialization circuit is further configured to control operation of the phase mixer depending on the programmed value.
6. A system, comprising:
a frequency divider configured to receive an input signal and generate a divided signal by dividing the frequency of the input signal by a value;
a delay line coupled to the frequency divider, the delay line configured to receive the divided signal from the frequency divider and delay the divided signal to generate an output signal; and
an initialization circuit coupled to the frequency divider and the delay line, the initialization circuit configured to determine the value based on a comparison of a period of the input signal relative to a time delay of the delay line.
7. The system of claim 6 wherein the initialization circuit is configured to determine the value based on a comparison of the period of the input signal relative to a minimum time delay of the delay line.
8. The system of claim 6 wherein the initialization circuit is configured to increase the value as the frequency of the input signal increases.
9. The system of claim 6 wherein the delay line includes a plurality of serially coupled delay stages each of which is configured successively delay the divided signal to generate respective delayed signals, and wherein the system further comprises a signal combiner coupled to the delay line, the signal combiner being configured to combine a first plurality of the delayed signals to generate a second plurality of output signals.
10. The system of claim 9 wherein the signal combiner is configured to increase the number of the delayed signals being combined to generate the output signals as the frequency of the input signal increases.
11. The system of claim 9 wherein the delay line is configured to adjust the magnitude of the delays provided by the delay stages so that that one of the delayed signals has a phase that is substantially equal to the phase of the input signal.
12. The system of claim 9 wherein the number of delayed signals in the first plurality is equal to the number of output signals in the second plurality.
13. The system of claim 9 wherein the signal combiner is configured to combine the first plurality of the delayed signals in a manner causing the plurality of output signals to have transitions that are coincident with transitions of the input signal.
14. The system of claim 6 wherein the value comprises an integer value.