Semiconductor device, design method and structure
A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation region. At least a first conductive line can comprise a semiconductor material formed over and in contact with the first diffusion region and the second diffusion region. A portion of the first conductive line in contact with the first diffusion region is doped to an opposite conductivity type as the first diffusion region. At least a second conductive line comprising a semiconductor material is formed in parallel with the first conductive line and over and in contact with the first diffusion region and the second diffusion region. A portion of the second conductive line can be in contact with the first diffusion region and doped to a same conductivity type as the first diffusion region. A portion of the second conductive line in contact with the second diffusion region can be doped to a same conductivity type as the second diffusion region.
1. A computer readable medium including at least a portion of an integrated circuit design, comprising:
at least a first section that represents at least a first junction field effect transistor (JFET) having at least three terminals;
at least a second section that represents at least a second JFET having at least three terminals;
at least a third section that represents an electrical connection between at least one of the terminals of the first JFET and one of the terminals of the second JFET; and
a common connection between one terminal of the first JFET, one terminal of the second JFET and the electrical connection form at least a portion of a single, essentially straight conductive line pattern.
2. The computer readable medium of claim 1 , wherein:
the first section, second section and third section represent cross-coupled transistors of a latch comprising two parallel conductive line patterns.
3. The computer readable medium of claim 2 , wherein:
the latch represents a portion of a static random access memory (SRAM) cell.
4. The computer readable medium of claim 3 , wherein:
the SRAM cell is selected from the group that includes four-transistor SRAM cells, six-transistor SRAM cells, and eight-transistor SRAM cells.
5. The computer readable medium of claim 1 , wherein:
the first section, second section and third section represent portions of a logic gate comprising three parallel conductive line patterns.
6. The computer readable medium of claim 5 , wherein:
the logic gate is selected from the group that includes a NAND gate and a NOR gate.
7. The computer readable medium of claim 1 , wherein:
the at least a third section includes
at least a first net that describes connections between circuit elements including at least one terminal of the first JFET, and
at least a second net that describes connections between circuit elements including at least one terminal of the second JFET.
8. The computer readable medium of claim 7 , wherein:
the first net includes
an active area mask data structure that defines at least two diffusion regions, and
a first portion of a JFET gate layer mask data structure that defines a first conductive line that intersects areas occupied by the two diffusion regions; and
the second net includes
the at least two diffusion regions of the active area mask data structure, and
a second portion of a JFET gate layer mask that defines a second conductive line that intersects areas occupied by the two diffusion regions.
9. The computer readable medium of claim 1 , wherein:
the first, second, and third sections each include representations of a semiconductor line section crossing over a substrate diffusion region section, with the semiconductor line sections being arranged into at least to contiguous columns, parallel to one another.
10. The computer readable medium of claim 1 , further including:
at least a fourth section that represents at least a first insulated gate field effect transistor (IGFET) having at least three terminals; and
at least a fifth section that represents an electrical connection between at least one of the terminals of the first IGFET.