Stacked transistors and process
View Patent ↗A method of horizontally stacking transistors on a common semiconductor substrate is initiated by providing a single crystal, generally silicon, semiconductor substrate. A plurality of transistors are formed on the single crystal semiconductor substrate and encapsulated in an insulating layer, such as silicon dioxide. One or more openings are formed through the insulating layer between the plurality of transistors so as to expose a surface of the single crystal semiconductor substrate. A layer of single crystal rare earth insulator material is epitaxially grown on the exposed surface of the single crystal semiconductor substrate. A layer of single crystal semiconductor material, generally silicon, is epitaxially grown on the layer of single crystal rare earth insulator material. An intermixed transistor is formed on the layer of single crystal semiconductor material.
1. A method of horizontally stacking or integrating transistors on a common semiconductor substrate comprising the steps of:
providing a single crystal semiconductor substrate;
forming a plurality of transistors on the single crystal semiconductor substrate;
encapsulating the plurality of transistors in an insulating layer;
forming an opening through the insulating layer between the plurality of transistors, the opening exposing a surface of the single crystal semiconductor substrate;
epitaxially growing a first layer of single crystal rare earth insulator material on the exposed surface of the single crystal semiconductor substrate, the first layer of single crystal rare earth insulator material being chosen to be substantially lattice matched with the single crystal semiconductor substrate;
epitaxially growing a first layer of single crystal semiconductor material on the first layer of single crystal rare earth insulator material, the first layer of single crystal semiconductor material being substantially lattice matched with the first layer of single crystal rare earth insulator material; and
forming an intermixed transistor on the first layer of single crystal semiconductor material.
2. A method as claimed in claim 1 wherein the step of forming the opening includes forming a plurality of openings, and the step of forming the intermixed transistor includes forming a plurality of intermixed transistors, one each in each of the plurality of openings.
3. A method as claimed in claim 2 wherein the step of forming the plurality of intermixed transistors includes forming intermixed transistors with one of different type and different conductivity from the plurality of transistors.
4. A method as claimed in claim 1 wherein the step of providing the single crystal semiconductor substrate includes providing a silicon substrate and the step of epitaxially growing the first layer of single crystal semiconductor material includes epitaxially growing a layer of single crystal silicon.
5. A method as claimed in claim 1 wherein the step of forming the intermixed transistor includes the steps of epitaxially growing a gate insulator layer of rare earth insulating material on the surface of the first layer of single crystal semiconductor material, epitaxially growing a gate stack layer on the gate insulator layer, etching the gate stack layer and the gate insulator layer to define a transistor gate with source and drain areas on opposite sides thereof, doping the source and drain areas to form a source and drain, and depositing metal contacts on the source, drain and gate stack.
6. A method of horizontally stacking or integrating transistors on a common semiconductor substrate comprising the steps of:
providing a single crystal semiconductor substrate;
forming a plurality of transistors on the single crystal semiconductor substrate;
encapsulating the plurality of transistors in an insulating layer;
forming an opening through the insulating layer between the plurality of transistors, the opening exposing a surface of the single crystal semiconductor substrate; and
epitaxially growing at least one layer combination of a single crystal rare earth conductive layer and a single crystal rare earth insulating layer on the exposed surface of the single crystal semiconductor substrate including epitaxially growing a gate insulator layer of rare earth insulating material on the surface of the first layer of single crystal semiconductor material, epitaxially growing a gate stack layer on the gate insulator layer, etching the gate stack layer and the gate insulator layer to define a transistor gate with source and drain areas on opposite sides thereof, doping the source and drain areas to form a source and drain, and depositing metal contacts on the source, drain and gate stack.
7. A method as claimed in claim 6 further including the steps of epitaxially growing a first layer of single crystal semiconductor material on the layer combination, and forming an intermixed transistor on the first layer of single crystal semiconductor material.
8. A method as claimed in claim 7 wherein the step of forming the opening includes forming a plurality of openings, and the step of forming the intermixed transistor includes forming a plurality of intermixed transistors, one each in each of the plurality of openings.
9. A method as claimed in claim 8 wherein the step of forming the plurality of intermixed transistors includes forming intermixed transistors with one of different type and different conductivity from the plurality of transistors.
10. A method as claimed in claim 7 wherein the step of providing the single crystal semiconductor substrate includes providing a silicon substrate and the step of epitaxially growing the first layer of single crystal semiconductor material includes epitaxially growing a layer of single crystal silicon.
11. A method as claimed in claim 6 further including the step of using the single crystal rare earth conductive layer of the layer combination to interconnect portions of the plurality of transistors.
12. A method as claimed in claim 6 further including the step of using the single crystal rare earth conductive layer of the layer combination to form inactive components of a circuit.