IP Library › Granted Patent US 7,969,490
Granted Patent B2
US 7,969,490 · App. 11/509,710 · Granted Jun 28, 2011

Method, apparatus, and system providing an imager with pixels having extended dynamic range

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,969,490
App. No.
11/509,710
Granted
Jun 28, 2011
Kind
B2
Abstract

The dynamic range of a pixel is increased by using selective photosensor resets during a frame time of image capture at a timing depending on the light intensity that the pixel will be exposed to during the frame time. Pixels that will be exposed to high light intensity are reset later in the frame than pixels that will be exposed to lower light intensity.

Claims (28)

1. An imager, comprising:

a pixel for providing an image output signal, said pixel comprising:

a photosensor for accumulating charge;

a storage region for storing charge transferred from the photosensor;

a transfer transistor for transferring charge from the photosensor to the storage region, wherein a drain of the transfer transistor is connected to the photosensor and a source of the transfer transistor is connected to the storage region;

a photosensor reset transistor connected between a selectively enabled control line and a gate of said transfer transistor, the photosensor reset transistor for transmitting a first control signal to a gate of the transfer transistor to reset the charge accumulated on the photosensor in accordance with said first control signal and a second control signal applied to a gate of said photosensor reset transistor.

2. The imager of claim 1 , further comprising a controller for delivering the first control signal to reset said photosensor during the frame time at a timing that corresponds to the value of light intensity sensed by the photosensor.

3. The imager of claim 1 , further comprising:

a reset transistor for resetting the charge on the storage region, wherein a drain of the reset transistor is connected to a supply voltage and a source of the reset transistor is connected to the storage region.

4. The imager of claim 1 , further comprising:

a source follower transistor for converting the charge stored in the storage region to a voltage, wherein a gate of the source follower transistor is connected to the storage region.

5. The imager of claim 4 , further comprising:

a row select transistor for outputting the voltage generated by the source follower transistor, wherein a drain of the row select transistor is connected to a source of the source follower transistor.

6. The imager of claim 1 , further comprising an array of said pixels.

7. a processor system, comprising:

a processor; and

an imager coupled to said processor, said imager comprising:

a pixel for providing an image output signal, said pixel comprising:

a photosensor for accumulating charge;

a storage region for storing charge transferred from the photosensor;

a transfer transistor for transferring charge from the photosensor to the storage region; and

a photosensor reset circuit for selectively resetting charge on said photosensor during an image capture period at a time related to a light level received by said photosensor; and

a photosensor reset transistor connected between a selectively enabled control line and a gate of said transfer transistor, the photosensor reset transistor for transmitting a first control signal to a gate of the transfer transistor to reset the charge accumulated on the photosensor in accordance with said first control signal and a second control signal applied to a gate of said photosensor reset transistor.

8. The processor system of claim 7 , wherein the processor system is a digital camera.

9. The processor system of claim 8 , wherein the digital camera is a still camera.

10. The processor system of claim 8 , wherein the digital camera is a video camera.

11. The processor system of claim 7 , further comprising a controller for controlling the photosensor reset circuit to reset the charge on said photosensor earlier in the image capture period if the light level is lower and later in the image capture period if the light level is higher.

12. The processor system of claim 7 , wherein the imager further comprises an array of said pixels.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2006
From: BOCK, NIKOLAI E.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 018213/0450 →
Continuity (1)
Related Publication 20080049133A1 · Feb 28, 2008