IP Library Granted Patent US 7,985,648
Granted Patent B2
US 7,985,648 · App. 12/717,753 · Granted Jul 26, 2011

Semiconductor memory device with bit line of small resistance and manufacturing method thereof

Assignee: Renesas Electronics Corporation
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Quick Facts
Patent No.
US 7,985,648
App. No.
12/717,753
Granted
Jul 26, 2011
Kind
B2
Abstract

A reduction of a resistance of a bit line of a memory cell array and a reduction of a forming area of the memory cell array are planed. Respective bit lines running at right angles to a word line are composed of a diffusion bit line formed in a semiconductor substrate and a linear metal bit line on an upper side of the diffusion bit line. The diffusion bit line is formed in a linear pattern on a lower side of the metal bit line in the same manner, and the metal bit line is connected with the diffusion bit line between the word lines. An interlayer insulating film is formed on the memory cell array, and the metal bit line is formed with being buried in it.

Claims (10)

1. A manufacturing method of a semiconductor memory device, comprising steps of:

(a) forming a gate insulating film on a semiconductor substrate and forming a resist having plural linear opening parts on said gate insulating film;

(b) removing said gate insulating film in a linear pattern by an etching employing said resist as a mask;

(c) forming a linear diffusion bit line in a semiconductor substrate by an ion implantation employing said resist as a mask;

(d) forming a linear third insulating film on an upper part of said diffusion bit line;

(e) forming plural linear word lines running at right angles to said diffusion bit line and having a first insulating film in its upper surface and a second insulating film in its side surface on said gate insulating film and said third insulating film;

(f) forming an interlayer insulating film on said word lines;

(g) forming a linear trench on an upper side of said diffusion bit line in said interlayer insulating film, removing said third insulating film between said word lines in said trench and exposing said diffusion bit line; and

(h) forming a linear metal bit line in said trench by filling up said trench with a predetermined metal.

2. The semiconductor memory device according to claim 1 , wherein said gate insulating film is an ONO film.

Assignments (1)
CHANGE OF NAME Recorded Sep 23, 2010
From: RENESAS TECHNOLOGY CORP.
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 025032/0799 →
Priority Claims (1)
JP 2003-287831 · Aug 6, 2003 · national
Continuity (3)
Division 11797406 · May 3, 2007
Division 10896060 · Jul 22, 2004
Related Publication 20100155822A1 · Jun 24, 2010