Floating source line architecture for non-volatile memory
A method and apparatus for writing data to a non-volatile memory cell, such as an RRAM memory cell. In some embodiments, a semiconductor array of non-volatile memory cells comprises a resistive sense element (RSE) and a switching device. A RSE of a plurality of memory cells is connected to a bit line while the switching device of a plurality of memory cells is connected to a word line and operated to select a memory cell. A source line is connected to the switching device and connects a series of memory cells together. Further, a driver circuit is connected to the bit line and writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSE connected to the selected source line.
1. An apparatus comprising:
a semiconductor array of non-volatile memory cells, each memory cell comprising a resistive sense element (RSE) and a switching device;
a bit line connected to the RSE of a plurality of memory cells;
a word line connected to the switching device of a plurality of memory cells and operated to select a memory cell;
a source line connected to the switching device and connecting a series of memory cells together, wherein the source line is not connected to a source ground or a source line transistor; and
a driver circuit connected to the bit line which writes a selected RSE of a selected source line to a selected resistive state by passing a write current along a write current path that passes through the selected RSE and through at least a portion of the remaining RSEs connected to the selected source line.
2. The apparatus of claim 1 , wherein the RSE is programmable to either a high resistance state or a low resistance state.
3. The apparatus of claim 1 , wherein the driver circuit comprises:
a bleeder transistor connected to the bit line;
a data transistor connected to the bit line;
a bleeder line operated to select the bleeder transistor;
a first data line connected to the bleeder transistor; and
a second data line connected to the data transistor and operated in a reverse polarity compared to the first data line.
4. The apparatus of claim 1 , wherein the series of memory cells connected by a source line and also connected to a common word line.
5. The apparatus of claim 1 , wherein the write current passes through the selected RSE in a first direction and passes through the remaining RSEs in is a direction opposite the first direction.
6. The apparatus of claim 5 , wherein the source line is connected to N memory cells where N is greater than or equal to three, the write current flows through the selected memory cell and concurrently flows through N−1 memory cells connected to different bit lines which are held at a common voltage potential.
7. The apparatus of claim 6 , wherein a magnitude of the write current passing through the remaining RSE is less than a magnitude of the write current passing through the selected RSE.
8. The apparatus of claim 1 , wherein the RSE comprises a magnetic random access memory (MRAM) element.
9. The apparatus of claim 1 , wherein the RSE comprises a resistive random access memory (RRAM) element.
10. A method comprising passing a write current along a write current path that flows through a selected resistive sense element (RSE) of a semiconductor array of non-volatile memory cells, wherein each memory cell comprises an RSE and a switching device; a bit line connected to the RSE of a plurality of memory cells; a word line connected to the switching device of a plurality of memory cells and operated to select a memory cell; a source line connected to the switching device and connecting a series of memory cells together, wherein the source line is not connected to a source ground or a source line transistor; and a driver circuit connected to the bit line that writes a selected RSE of a selected source line to a selected resistive state by passing the write current through at least a portion of the remaining RSE connected to the selected source line.
11. The method of claim 10 , wherein the selected RSE is programmable to either a high resistance state or a low resistance state.
12. The method of claim 10 , wherein the driver circuit comprises:
a bleeder transistor connected to the bit line;
a data transistor connected to the bit line;
a bleeder line operated to select the bleeder transistor;
a first data line connected to the bleeder transistor; and
a second data line connected to the data transistor and operated in a reverse polarity compared to the first data line.
13. The method of claim 10 , wherein the series of memory cells connected by a source line and also connected to a common word line.
14. The method of claim 10 , wherein the write current passes through the selected RSE in a first direction and passes through the remaining RSEs in a direction opposite the first direction.
15. The method of claim 14 , wherein the source line is connected to N memory cells where N is greater than or equal to three, the write current flows through the selected memory cell and concurrently flows through N−1 memory cells connected to different bit lines held at a common voltage potential.
16. A storage device comprising:
a plurality of N non-volatile memory cells where N is greater than two, each memory cell comprising a programmable resistive sense element (RSE) connected in series with a switching device between a separate bit line and a common floating source line; and
a control circuit which programs a selected memory cell of said plurality to a selected state by passing a write current through the selected memory cell and along the common floating source line, the write current concurrently passing in parallel through the remaining N−1 memory cells of said plurality, wherein during said programming the bit line connected to the selected memory cell is held at a first voltage potential and the remaining bit lines connected to the respective remaining N−1 memory cells are held at a different, common second potential.
17. The storage device of claim 16 , in which the floating source line is not connected to a source ground or a source line transistor.
18. The storage device of claim 16 , in which the switching devices of the plurality of N memory cells are connected to a common word line.
19. The storage device of claim 16 , in which the first voltage potential is characterized as a positive voltage and the second voltage potential is characterized as electrical ground.
20. The storage device of claim 16 , in which each RSE is characterized as a magnetic random access memory (MRAM) element and each switching device is characterized as a transistor.