Method and circuit for eFuse protection
An eFuse (electronic fuse) circuit has a first detector for determining whether an ESD (electrostatic discharge) event occurs at a circuit pad of an integrated circuit and provides an ESD trigger signal in response thereto. A second detector detects a presence of a first power supply voltage and provides a power on signal indicating the presence of the first power supply voltage. A fuse is permitted to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected. The fuse is not permitted to be programmed when an ESD event is detected or when there is an absence of the power on signal. An array of fuses is thereby protected from inadvertent programming from an ESD event or powering up an integrated circuit.
1. An eFuse protection circuit comprising:
a first detection circuit coupled to a circuit pad for detecting an ESD event and having an output for providing an ESD trigger signal in response thereto;
a second detection circuit coupled to a first power supply voltage terminal for detecting a presence of a first power supply voltage and having an output for providing a power on signal indicating the presence of the first power supply voltage;
a switching control circuit having a first input coupled to the output of the first detection circuit, a second input coupled to the output of the second detection circuit and an output for providing a control signal; and
at least one fuse coupled to the switching control circuit, programming of the at least one fuse being permitted in response to the control signal, the control signal being coupled to the at least one fuse by the switching control circuit if no detection of the ESD event occurs and no absence of the power on signal is detected.
2. The eFuse protection circuit of claim 1 further comprising:
a buffer circuit coupled between the switching control circuit and the at least one fuse, the buffer circuit having an input for receiving and amplifying a voltage magnitude of the control signal and providing a fuse program voltage to the at least one fuse in response thereto.
3. The eFuse protection circuit of claim 2 wherein the switching control circuit further comprises:
a multiple input logic gate having a first input for receiving the ESD trigger signal, a second input for receiving the power on signal, a third input for receiving a fuse program enable signal, and an output for providing the control signal in an active state when the fuse program signal is asserted, no ESD event is detected and the first power supply voltage is indicated to be present.
4. The eFuse protection circuit of claim 3 wherein the switching control circuit further comprises:
circuitry powered by the first power supply voltage, the circuitry having an input for receiving the fuse program enable signal and buffering the fuse program enable signal.
5. The eFuse protection circuit of claim 4 wherein the switching control circuit further comprises:
a level shifter powered by a second power supply voltage having an input coupled to an output of the circuitry powered by the first power supply voltage, the level shifter providing a shifted form of the fuse program enable signal.
6. The eFuse protection circuit of claim 5 wherein the second detection circuit further comprises:
a comparison and level shifting circuit having a power terminal for receiving the second power supply voltage, an input terminal for receiving the first power supply voltage, and an output; and
an inverter having an input coupled to the output of the comparison and level shifting circuit, and an output for providing the power on signal, the inverter having a power terminal for receiving the second power supply voltage.
7. The eFuse protection circuit of claim 6 wherein the at least one fuse is a plurality of fuses, each fuse of the plurality being coupled in series with a select transistor controlled by a respective different select signal, each series-coupled fuse and select transistor being coupled between a first terminal for receiving the fuse program voltage and a second terminal for receiving a reference voltage.
8. The eFuse protection circuit of claim 7 wherein the circuit pad is a power supply pad of an integrated circuit, the integrated circuit including the eFuse protection circuit.
9. A method comprising:
providing a first detector for determining whether an ESD event occurs at a circuit pad of an integrated circuit and providing an ESD trigger signal in response thereto;
providing a second detector for detecting a presence of a first power supply voltage and providing a power on signal indicating the presence of the first power supply voltage; and
permitting a fuse to be programmable when no detection of the ESD event occurs and at the same time a presence of the power on signal is detected, said fuse not being permitted to be programmed when an ESD event is detected or in an absence of the power on signal.
10. The method of claim 9 further comprising:
providing a switching control circuit having a first input coupled to an output of the first detector, a second input coupled to the output of the second detector and an output for providing a control signal.
11. The method of claim 10 further comprising:
coupling a buffer circuit between the switching control circuit and the fuse, the buffer circuit having an input for receiving and amplifying a voltage magnitude of the control signal and providing a fuse program voltage to the fuse in response thereto.
12. The method of claim 9 further comprising:
providing a multiple input logic gate having a first input for receiving the ESD trigger signal, a second input for receiving the power on signal, a third input for receiving a fuse program enable signal, and an output for providing the control signal in an active state when the fuse program signal is asserted, no ESD event is detected and the first power supply voltage is indicated to be present.
13. The method of claim 12 further comprising:
buffering and level shifting the fuse program enable signal before coupling the fuse program enable signal to the third input of the multiple input logic gate.
14. The method of claim 9 further comprising:
implementing the circuit pad as a voltage pad for receiving a second supply voltage, the second supply voltage having a magnitude that is greater than the first supply voltage and being used to derive a program voltage for the fuse.
15. A circuit, comprising:
a power supply detection circuit for detecting a presence within the circuit of a first power supply voltage, the power supply detection circuit providing a power on signal when the first power supply voltage is present in the circuit;
an ESD detection circuit coupled to a circuit pad for receiving a second power supply voltage, the ESD detection circuit detecting an ESD event at the circuit pad and providing an ESD signal in response to the detecting;
a switching control circuit having a first input coupled to the power supply detection circuit, a second input coupled to the ESD detection circuit, a third input coupled to a program enable signal, and an output for providing a control signal to permit fuse programming when no ESD event is detected, the first power supply voltage is detected and the program enable signal is asserted; and
a fuse array coupled to the switching control circuit, the fuse array comprising a plurality of fuses each coupled in series with a respective select transistor between a program voltage terminal and a reference voltage terminal, the fuse array being selectively programmed in response to the control signal.
16. The circuit of claim 15 further comprising:
a buffer circuit having an input coupled to the output of the switching control circuit and an output coupled to the program voltage terminal of the fuse array, the buffer circuit buffering the control signal to provide a fuse program supply voltage to program voltage terminal of the fuse array.
17. The circuit of claim 15 wherein the switching control circuit further comprises:
a NOR logic gate having a first input coupled to the first input of the switching control circuit, a second input coupled to the second input of the switching control circuit, a third input coupled to the third input of the switching control circuit, and an output for providing the control signal in an active state when the fuse program signal is asserted, no ESD event is detected and the first power supply voltage is indicated to be present.
18. The circuit of claim 17 wherein the switching control circuit further comprises:
circuitry powered by the first power supply voltage, the circuitry having an input for receiving the program enable signal and buffering the program enable signal; and
a level shifter powered by a second power supply voltage having an input coupled to an output of the circuitry powered by the first power supply voltage, the level shifter providing a shifted form of the program enable signal.
19. The circuit of claim 15 wherein the power supply detection circuit further comprises:
a comparison and level shifting circuit coupled to the first power supply voltage and the second power supply voltage, the comparison and level shifting circuit comparing a voltage magnitude of the first power supply voltage to a known voltage value that is dependent on the first power supply voltage to determine if the first power supply voltage is on.
20. The circuit of claim 15 wherein the plurality of fuses comprise polysilicon fuses that are programmed with a program voltage value of no greater than 3.3 volts.