Solid-state imaging device
A solid-state imaging device has a substrate in which are formed a pixel array portion having a plurality of pixels, and a peripheral circuitry portion. The device is characterized in that a first multilevel metallization structure is formed over the peripheral circuitry portion, and a second multilevel metallization structure thinner than the first multilevel metallization structure is formed over the pixel array portion.
1. A solid-state imaging device comprising:
a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a peripheral circuitry portion peripheral to the pixel array portion;
a first multilevel metallization structure including first multilevel connection layers, first multilevel dielectric layers therebetween, and first multilevel conductive vias formed in the first multilevel dielectric lavers for connecting the first multilevel connection layers to each other, and formed over the peripheral circuitry portion; and
a second multilevel metallization structure including second multilevel connection layers, second multilevel dielectric layers therebetween, and second multilevel conductive vias formed in the second multilevel dielectric lavers for connecting the second multilevel connection lavers to each other, being thinner than the first multilevel metallization structure, and formed over the pixel array portion.
2. The solid-state imaging device according to claim 1 , wherein
a single trench structure is formed over the pixel array portion, the single trench structure being formed by the first multilevel metallization structure formed over the peripheral circuitry portion and the second multilevel metallization structure formed over the pixel array portion, and the trench structure has a protrusion in at least one corner thereof, and
the device further comprising a color filter film formed on a bottom of the trench structure by spin coating and a microlens over each pixel.
3. The solid-state imaging device according to claim 1 , wherein
a single trench structure is formed over the pixel array portion, the single trench structure being formed by the first multilevel metallization structure formed over the peripheral circuitry portion and the second multilevel metallization structure formed over the pixel array portion, the trench structure extends over a region that includes at least part of the pixel array portion.
4. The solid-state imaging device according to claim 3 , wherein the trench structure region coincides with a central light-receiving pixel region of the pixel array portion that excludes peripheral black pixels.
5. The solid-state imaging device according to claim 3 , wherein
the trench structure region is wider than a central light-receiving pixel region of the pixel array portion that excludes peripheral black pixels.
6. The solid-state imaging device according to claim 1 , wherein
a single trench structure is formed over the pixel array portion, the single trench structure being formed by the first multilevel metallization structure formed over the peripheral circuitry portion and the second multilevel metallization structure formed over the pixel array portion, an optical color filter film is formed within the trench structure, a microlens for each pixel is formed over the optical color filter film, and the optical color filter film has a thickness which is substantially equal to the depth of the trench structure.
7. The solid-state imaging device according to claim 1 , wherein
a single trench structure is formed over the pixel array portion, the single trench structure being formed by the first multilevel metallization structure formed over the peripheral circuitry portion and the second multilevel metallization structure formed over the pixel array portion, an optical color filter film is formed within the trench structure, a microlens for each pixel is formed over the optical color filter film, and the optical color filter film has a thickness which is smaller than the depth of the trench structure.
8. A solid-state imaging device comprising:
a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a periphery circuitry portion peripheral to the pixel array portion;
a first multilevel metallization structure which is formed over the peripheral circuitry portion and has a plurality of first connection layers, a plurality of first dielectric layers therebetween and a plurality of first vias for connecting the first connection layers to each other; and
a second multilevel metallization structure which is formed over the pixel array portion and has a smaller number of second connection layers than the first multilevel metallization structure, a plurality of second connection layers therebetween and a plurality of second vias for connecting the second connection layers to each other.
9. A solid-state imaging device comprising:
a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a periphery circuitry portion peripheral to the pixel array portion;
a first multilevel metallization structure which is formed over the peripheral circuitry portion and has a plurality of first connection layers, a plurality of first dielectric layers therebetween and a plurality of first vias for connecting the first connection layers to each other; and
a second multilevel metallization structure which is formed over the pixel array portion and has a smaller number of second connection layers than the first multilevel metallization structure, a plurality of second dielectric layers therebetween and a plurality of second vias for connecting the second connection layers to each other, over which a color filter film is formed at a level corresponding to the uppermost level of the first multilevel metallization structure.
10. The solid-state imaging device according to claim 4 , wherein the pixel array portion includes the central light-receiving pixel region and the peripheral black pixels located outside of the central light-receiving pixel region.
11. The solid-state imaging device according to claim 5 , wherein the pixel array portion includes the central light-receiving pixel region and the peripheral black pixels located outside of the central light-receiving pixel region.
12. The solid-state imaging device according to claim 1 , wherein the number of the second multilevel connection layers is lower than the number of the first multilevel connection layers.
13. The solid-state imaging device according to claim 1 , wherein said transistor in each of the pixel includes a transfer transistor connected to the photo-electric converter.
14. The solid-state imaging device according to claim 8 , wherein said transistor in each of the pixel includes a transfer transistor connected to the photo-electric converter.
15. The solid-state imaging device according to claim 9 , wherein said transistor in each of the pixel includes a transfer transistor connected to the photo-electric converter.
16. The solid-state imaging device according to claim 1 , wherein said peripheral circuit portion includes an analog circuit.
17. The solid-state imaging device according to claim 8 , wherein said peripheral circuit portion includes an analog circuit.
18. The solid-state imaging device according to claim 9 , wherein said peripheral circuit portion includes an analog circuit.
19. A solid-state imaging device comprising:
a substrate in which are formed a pixel array portion having a plurality of pixels each of which includes a photo-electric converter and a transistor, and a peripheral circuitry portion peripheral to the pixel array portion;
a first multilevel connection layers structure including first connection layers, first dielectric layers therebetween and first vias for connecting the first connection layers to each other, and formed over the peripheral circuitry portion; and
a second multilevel connecting layers structure including second connection layers, second dielectric layers therebetween and second vias for connecting the second connection lavers to each other, and formed over the pixel array portion,
wherein the thickness of the first dielectric layers of the first multilevel connection layers structure is thinner than the thickness of the second dielectric layers of the second multilevel connection layers structure.